License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
2008-05-19 23:52:27 +00:00
|
|
|
/*
|
2005-04-16 22:20:36 +00:00
|
|
|
* rtrap.S: Preparing for return from trap on Sparc V9.
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
|
|
|
|
|
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#include <asm/asi.h>
|
|
|
|
|
#include <asm/pstate.h>
|
|
|
|
|
#include <asm/ptrace.h>
|
|
|
|
|
#include <asm/spitfire.h>
|
|
|
|
|
#include <asm/head.h>
|
|
|
|
|
#include <asm/visasm.h>
|
|
|
|
|
#include <asm/processor.h>
|
|
|
|
|
|
2013-09-14 12:02:11 +00:00
|
|
|
#ifdef CONFIG_CONTEXT_TRACKING
|
|
|
|
|
# define SCHEDULE_USER schedule_user
|
|
|
|
|
#else
|
|
|
|
|
# define SCHEDULE_USER schedule
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
.text
|
|
|
|
|
.align 32
|
|
|
|
|
__handle_preemption:
|
2013-09-14 12:02:11 +00:00
|
|
|
call SCHEDULE_USER
|
2018-02-23 22:46:41 +00:00
|
|
|
661: wrpr %g0, RTRAP_PSTATE, %pstate
|
|
|
|
|
/* If userspace is using ADI, it could potentially pass
|
|
|
|
|
* a pointer with version tag embedded in it. To maintain
|
|
|
|
|
* the ADI security, we must re-enable PSTATE.mcde before
|
|
|
|
|
* we continue execution in the kernel for another thread.
|
|
|
|
|
*/
|
|
|
|
|
.section .sun_m7_1insn_patch, "ax"
|
|
|
|
|
.word 661b
|
|
|
|
|
wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
|
|
|
|
|
.previous
|
2005-04-16 22:20:36 +00:00
|
|
|
ba,pt %xcc, __handle_preemption_continue
|
|
|
|
|
wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
|
|
|
|
|
|
|
|
|
|
__handle_user_windows:
|
2018-10-26 03:36:46 +00:00
|
|
|
add %sp, PTREGS_OFF, %o0
|
2005-04-16 22:20:36 +00:00
|
|
|
call fault_in_user_windows
|
2018-02-23 22:46:41 +00:00
|
|
|
661: wrpr %g0, RTRAP_PSTATE, %pstate
|
|
|
|
|
/* If userspace is using ADI, it could potentially pass
|
|
|
|
|
* a pointer with version tag embedded in it. To maintain
|
|
|
|
|
* the ADI security, we must re-enable PSTATE.mcde before
|
|
|
|
|
* we continue execution in the kernel for another thread.
|
|
|
|
|
*/
|
|
|
|
|
.section .sun_m7_1insn_patch, "ax"
|
|
|
|
|
.word 661b
|
|
|
|
|
wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
|
|
|
|
|
.previous
|
2010-09-24 04:52:52 +00:00
|
|
|
ba,pt %xcc, __handle_preemption_continue
|
|
|
|
|
wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
__handle_userfpu:
|
|
|
|
|
rd %fprs, %l5
|
|
|
|
|
andcc %l5, FPRS_FEF, %g0
|
|
|
|
|
sethi %hi(TSTATE_PEF), %o0
|
|
|
|
|
be,a,pn %icc, __handle_userfpu_continue
|
|
|
|
|
andn %l1, %o0, %l1
|
|
|
|
|
ba,a,pt %xcc, __handle_userfpu_continue
|
|
|
|
|
|
|
|
|
|
__handle_signal:
|
2006-01-19 10:42:49 +00:00
|
|
|
mov %l5, %o1
|
|
|
|
|
add %sp, PTREGS_OFF, %o0
|
2008-04-24 10:15:22 +00:00
|
|
|
mov %l0, %o2
|
2005-04-16 22:20:36 +00:00
|
|
|
call do_notify_resume
|
2018-02-23 22:46:41 +00:00
|
|
|
661: wrpr %g0, RTRAP_PSTATE, %pstate
|
|
|
|
|
/* If userspace is using ADI, it could potentially pass
|
|
|
|
|
* a pointer with version tag embedded in it. To maintain
|
|
|
|
|
* the ADI security, we must re-enable PSTATE.mcde before
|
|
|
|
|
* we continue execution in the kernel for another thread.
|
|
|
|
|
*/
|
|
|
|
|
.section .sun_m7_1insn_patch, "ax"
|
|
|
|
|
.word 661b
|
|
|
|
|
wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
|
|
|
|
|
.previous
|
2005-04-16 22:20:36 +00:00
|
|
|
wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
|
|
|
|
|
|
|
|
|
|
/* Signal delivery can modify pt_regs tstate, so we must
|
|
|
|
|
* reload it.
|
|
|
|
|
*/
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
|
|
|
|
|
sethi %hi(0xf << 20), %l4
|
|
|
|
|
and %l1, %l4, %l4
|
2018-10-15 03:22:28 +00:00
|
|
|
andn %l1, %l4, %l1
|
2010-09-24 04:52:52 +00:00
|
|
|
ba,pt %xcc, __handle_preemption_continue
|
2018-10-15 03:22:28 +00:00
|
|
|
srl %l4, 20, %l4
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2008-11-26 06:24:59 +00:00
|
|
|
/* When returning from a NMI (%pil==15) interrupt we want to
|
|
|
|
|
* avoid running softirqs, doing IRQ tracing, preempting, etc.
|
|
|
|
|
*/
|
|
|
|
|
.globl rtrap_nmi
|
|
|
|
|
rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
|
|
|
|
|
sethi %hi(0xf << 20), %l4
|
|
|
|
|
and %l1, %l4, %l4
|
|
|
|
|
andn %l1, %l4, %l1
|
|
|
|
|
srl %l4, 20, %l4
|
|
|
|
|
ba,pt %xcc, rtrap_no_irq_enable
|
2015-12-22 04:48:03 +00:00
|
|
|
nop
|
|
|
|
|
/* Do not actually set the %pil here. We will do that
|
|
|
|
|
* below after we clear PSTATE_IE in the %pstate register.
|
|
|
|
|
* If we re-enable interrupts here, we can recurse down
|
|
|
|
|
* the hardirq stack potentially endlessly, causing a
|
|
|
|
|
* stack overflow.
|
|
|
|
|
*/
|
2008-11-26 06:24:59 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
.align 64
|
2008-04-24 10:15:22 +00:00
|
|
|
.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
|
2005-04-16 22:20:36 +00:00
|
|
|
rtrap_irq:
|
|
|
|
|
rtrap:
|
|
|
|
|
/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
|
2012-04-13 20:56:46 +00:00
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
|
2005-04-16 22:20:36 +00:00
|
|
|
rtrap_xcall:
|
|
|
|
|
sethi %hi(0xf << 20), %l4
|
|
|
|
|
and %l1, %l4, %l4
|
2006-11-16 21:38:57 +00:00
|
|
|
andn %l1, %l4, %l1
|
|
|
|
|
srl %l4, 20, %l4
|
|
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
|
|
|
brnz,pn %l4, rtrap_no_irq_enable
|
|
|
|
|
nop
|
|
|
|
|
call trace_hardirqs_on
|
|
|
|
|
nop
|
2010-04-20 07:48:37 +00:00
|
|
|
/* Do not actually set the %pil here. We will do that
|
|
|
|
|
* below after we clear PSTATE_IE in the %pstate register.
|
|
|
|
|
* If we re-enable interrupts here, we can recurse down
|
|
|
|
|
* the hardirq stack potentially endlessly, causing a
|
|
|
|
|
* stack overflow.
|
|
|
|
|
*
|
|
|
|
|
* It is tempting to put this test and trace_hardirqs_on
|
|
|
|
|
* call at the 'rt_continue' label, but that will not work
|
|
|
|
|
* as that path hits unconditionally and we do not want to
|
|
|
|
|
* execute this in NMI return paths, for example.
|
|
|
|
|
*/
|
2006-11-16 21:38:57 +00:00
|
|
|
#endif
|
2008-11-26 06:24:59 +00:00
|
|
|
rtrap_no_irq_enable:
|
2006-11-16 21:38:57 +00:00
|
|
|
andcc %l1, TSTATE_PRIV, %l3
|
2005-04-16 22:20:36 +00:00
|
|
|
bne,pn %icc, to_kernel
|
2006-11-16 21:38:57 +00:00
|
|
|
nop
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
/* We must hold IRQs off and atomically test schedule+signal
|
|
|
|
|
* state, then hold them off all the way back to userspace.
|
2006-11-16 21:38:57 +00:00
|
|
|
* If we are returning to kernel, none of this matters. Note
|
|
|
|
|
* that we are disabling interrupts via PSTATE_IE, not using
|
|
|
|
|
* %pil.
|
2005-04-16 22:20:36 +00:00
|
|
|
*
|
|
|
|
|
* If we do not do this, there is a window where we would do
|
|
|
|
|
* the tests, later the signal/resched event arrives but we do
|
|
|
|
|
* not process it since we are still in kernel mode. It would
|
|
|
|
|
* take until the next local IRQ before the signal/resched
|
|
|
|
|
* event would be handled.
|
|
|
|
|
*
|
2010-03-03 16:08:49 +00:00
|
|
|
* This also means that if we have to deal with user
|
|
|
|
|
* windows, we have to redo all of these sched+signal checks
|
|
|
|
|
* with IRQs disabled.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
|
to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
|
|
|
|
|
wrpr 0, %pil
|
|
|
|
|
__handle_preemption_continue:
|
|
|
|
|
ldx [%g6 + TI_FLAGS], %l0
|
|
|
|
|
sethi %hi(_TIF_USER_WORK_MASK), %o0
|
|
|
|
|
or %o0, %lo(_TIF_USER_WORK_MASK), %o0
|
|
|
|
|
andcc %l0, %o0, %g0
|
|
|
|
|
sethi %hi(TSTATE_PEF), %o0
|
|
|
|
|
be,pt %xcc, user_nowork
|
|
|
|
|
andcc %l1, %o0, %g0
|
|
|
|
|
andcc %l0, _TIF_NEED_RESCHED, %g0
|
|
|
|
|
bne,pn %xcc, __handle_preemption
|
2008-04-20 22:06:49 +00:00
|
|
|
andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
|
2005-04-16 22:20:36 +00:00
|
|
|
bne,pn %xcc, __handle_signal
|
|
|
|
|
ldub [%g6 + TI_WSAVED], %o2
|
|
|
|
|
brnz,pn %o2, __handle_user_windows
|
|
|
|
|
nop
|
|
|
|
|
sethi %hi(TSTATE_PEF), %o0
|
2010-03-03 16:08:49 +00:00
|
|
|
andcc %l1, %o0, %g0
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
/* This fpdepth clear is necessary for non-syscall rtraps only */
|
|
|
|
|
user_nowork:
|
|
|
|
|
bne,pn %xcc, __handle_userfpu
|
|
|
|
|
stb %g0, [%g6 + TI_FPDEPTH]
|
|
|
|
|
__handle_userfpu_continue:
|
|
|
|
|
|
|
|
|
|
rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
|
|
|
|
|
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
|
2006-02-27 07:24:22 +00:00
|
|
|
brz,pt %l3, 1f
|
2006-02-06 05:59:03 +00:00
|
|
|
mov %g6, %l2
|
|
|
|
|
|
2006-02-27 07:24:22 +00:00
|
|
|
/* Must do this before thread reg is clobbered below. */
|
2006-02-03 05:55:10 +00:00
|
|
|
LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
|
2006-02-01 02:29:18 +00:00
|
|
|
1:
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
|
2005-04-16 22:20:36 +00:00
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
|
2006-02-06 05:29:28 +00:00
|
|
|
|
|
|
|
|
/* Normal globals are restored, go to trap globals. */
|
|
|
|
|
661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
|
2006-02-17 00:23:45 +00:00
|
|
|
nop
|
|
|
|
|
.section .sun4v_2insn_patch, "ax"
|
2006-02-06 05:29:28 +00:00
|
|
|
.word 661b
|
2006-02-17 00:23:45 +00:00
|
|
|
wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
|
2006-02-06 05:29:28 +00:00
|
|
|
SET_GL(1)
|
|
|
|
|
.previous
|
|
|
|
|
|
2006-02-06 05:59:03 +00:00
|
|
|
mov %l2, %g6
|
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
|
|
|
|
|
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
|
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
|
|
|
|
|
|
|
|
|
|
ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
|
|
|
|
|
wr %o3, %g0, %y
|
|
|
|
|
wrpr %l4, 0x0, %pil
|
|
|
|
|
wrpr %g0, 0x1, %tl
|
sparc: Fix debugger syscall restart interactions.
So, forever, we've had this ptrace_signal_deliver implementation
which tries to handle all of the nasties that can occur when the
debugger looks at a process about to take a signal. It's meant
to address all of these issues inside of the kernel so that the
debugger need not be mindful of such things.
Problem is, this doesn't work.
The idea was that we should do the syscall restart business first, so
that the debugger captures that state. Otherwise, if the debugger for
example saves the child's state, makes the child execute something
else, then restores the saved state, we won't handle the syscall
restart properly because we lose the "we're in a syscall" state.
The code here worked for most cases, but if the debugger actually
passes the signal through to the child unaltered, it's possible that
we would do a syscall restart when we shouldn't have.
In particular this breaks the case of debugging a process under a gdb
which is being debugged by yet another gdb. gdb uses sigsuspend
to wait for SIGCHLD of the inferior, but if gdb itself is being
debugged by a top-level gdb we get a ptrace_stop(). The top-level gdb
does a PTRACE_CONT with SIGCHLD to let the inferior gdb see the
signal. But ptrace_signal_deliver() assumed the debugger would cancel
out the signal and therefore did a syscall restart, because the return
error was ERESTARTNOHAND.
Fix this by simply making ptrace_signal_deliver() a nop, and providing
a way for the debugger to control system call restarting properly:
1) Report a "in syscall" software bit in regs->{tstate,psr}.
It is set early on in trap entry to a system call and is fully
visible to the debugger via ptrace() and regsets.
2) Test this bit right before doing a syscall restart. We have
to do a final recheck right after get_signal_to_deliver() in
case the debugger cleared the bit during ptrace_stop().
3) Clear the bit in trap return so we don't accidently try to set
that bit in the real register.
As a result we also get a ptrace_{is,clear}_syscall() for sparc32 just
like sparc64 has.
M68K has this same exact bug, and is now the only other user of the
ptrace_signal_deliver hook. It needs to be fixed in the same exact
way as sparc.
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-05-11 09:07:19 +00:00
|
|
|
andn %l1, TSTATE_SYSCALL, %l1
|
2005-04-16 22:20:36 +00:00
|
|
|
wrpr %l1, %g0, %tstate
|
|
|
|
|
wrpr %l2, %g0, %tpc
|
|
|
|
|
wrpr %o2, %g0, %tnpc
|
|
|
|
|
|
|
|
|
|
brnz,pn %l3, kern_rtt
|
|
|
|
|
mov PRIMARY_CONTEXT, %l7
|
2006-02-08 06:13:05 +00:00
|
|
|
|
|
|
|
|
661: ldxa [%l7 + %l7] ASI_DMMU, %l0
|
|
|
|
|
.section .sun4v_1insn_patch, "ax"
|
|
|
|
|
.word 661b
|
|
|
|
|
ldxa [%l7 + %l7] ASI_MMU, %l0
|
|
|
|
|
.previous
|
|
|
|
|
|
2005-10-04 22:23:20 +00:00
|
|
|
sethi %hi(sparc64_kern_pri_nuc_bits), %l1
|
|
|
|
|
ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
|
2005-04-16 22:20:36 +00:00
|
|
|
or %l0, %l1, %l0
|
2006-02-08 06:13:05 +00:00
|
|
|
|
|
|
|
|
661: stxa %l0, [%l7] ASI_DMMU
|
|
|
|
|
.section .sun4v_1insn_patch, "ax"
|
|
|
|
|
.word 661b
|
|
|
|
|
stxa %l0, [%l7] ASI_MMU
|
|
|
|
|
.previous
|
|
|
|
|
|
2006-02-01 02:33:00 +00:00
|
|
|
sethi %hi(KERNBASE), %l7
|
|
|
|
|
flush %l7
|
2005-04-16 22:20:36 +00:00
|
|
|
rdpr %wstate, %l1
|
|
|
|
|
rdpr %otherwin, %l2
|
|
|
|
|
srl %l1, 3, %l1
|
|
|
|
|
|
2017-08-18 19:40:36 +00:00
|
|
|
661: wrpr %l2, %g0, %canrestore
|
|
|
|
|
.section .fast_win_ctrl_1insn_patch, "ax"
|
|
|
|
|
.word 661b
|
|
|
|
|
.word 0x89880000 ! normalw
|
|
|
|
|
.previous
|
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
wrpr %l1, %g0, %wstate
|
2006-02-04 08:10:01 +00:00
|
|
|
brnz,pt %l2, user_rtt_restore
|
2017-08-18 19:40:36 +00:00
|
|
|
661: wrpr %g0, %g0, %otherwin
|
|
|
|
|
.section .fast_win_ctrl_1insn_patch, "ax"
|
|
|
|
|
.word 661b
|
|
|
|
|
nop
|
|
|
|
|
.previous
|
2006-02-04 08:10:01 +00:00
|
|
|
|
|
|
|
|
ldx [%g6 + TI_FLAGS], %g3
|
|
|
|
|
wr %g0, ASI_AIUP, %asi
|
|
|
|
|
rdpr %cwp, %g1
|
|
|
|
|
andcc %g3, _TIF_32BIT, %g0
|
|
|
|
|
sub %g1, 1, %g1
|
|
|
|
|
bne,pt %xcc, user_rtt_fill_32bit
|
|
|
|
|
wrpr %g1, %cwp
|
|
|
|
|
ba,a,pt %xcc, user_rtt_fill_64bit
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 20:52:21 +00:00
|
|
|
nop
|
2006-02-04 08:10:01 +00:00
|
|
|
|
sparc64: Fix return from trap window fill crashes.
We must handle data access exception as well as memory address unaligned
exceptions from return from trap window fill faults, not just normal
TLB misses.
Otherwise we can get an OOPS that looks like this:
ld-linux.so.2(36808): Kernel bad sw trap 5 [#1]
CPU: 1 PID: 36808 Comm: ld-linux.so.2 Not tainted 4.6.0 #34
task: fff8000303be5c60 ti: fff8000301344000 task.ti: fff8000301344000
TSTATE: 0000004410001601 TPC: 0000000000a1a784 TNPC: 0000000000a1a788 Y: 00000002 Not tainted
TPC: <do_sparc64_fault+0x5c4/0x700>
g0: fff8000024fc8248 g1: 0000000000db04dc g2: 0000000000000000 g3: 0000000000000001
g4: fff8000303be5c60 g5: fff800030e672000 g6: fff8000301344000 g7: 0000000000000001
o0: 0000000000b95ee8 o1: 000000000000012b o2: 0000000000000000 o3: 0000000200b9b358
o4: 0000000000000000 o5: fff8000301344040 sp: fff80003013475c1 ret_pc: 0000000000a1a77c
RPC: <do_sparc64_fault+0x5bc/0x700>
l0: 00000000000007ff l1: 0000000000000000 l2: 000000000000005f l3: 0000000000000000
l4: fff8000301347e98 l5: fff8000024ff3060 l6: 0000000000000000 l7: 0000000000000000
i0: fff8000301347f60 i1: 0000000000102400 i2: 0000000000000000 i3: 0000000000000000
i4: 0000000000000000 i5: 0000000000000000 i6: fff80003013476a1 i7: 0000000000404d4c
I7: <user_rtt_fill_fixup+0x6c/0x7c>
Call Trace:
[0000000000404d4c] user_rtt_fill_fixup+0x6c/0x7c
The window trap handlers are slightly clever, the trap table entries for them are
composed of two pieces of code. First comes the code that actually performs
the window fill or spill trap handling, and then there are three instructions at
the end which are for exception processing.
The userland register window fill handler is:
add %sp, STACK_BIAS + 0x00, %g1; \
ldxa [%g1 + %g0] ASI, %l0; \
mov 0x08, %g2; \
mov 0x10, %g3; \
ldxa [%g1 + %g2] ASI, %l1; \
mov 0x18, %g5; \
ldxa [%g1 + %g3] ASI, %l2; \
ldxa [%g1 + %g5] ASI, %l3; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %l4; \
ldxa [%g1 + %g2] ASI, %l5; \
ldxa [%g1 + %g3] ASI, %l6; \
ldxa [%g1 + %g5] ASI, %l7; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %i0; \
ldxa [%g1 + %g2] ASI, %i1; \
ldxa [%g1 + %g3] ASI, %i2; \
ldxa [%g1 + %g5] ASI, %i3; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %i4; \
ldxa [%g1 + %g2] ASI, %i5; \
ldxa [%g1 + %g3] ASI, %i6; \
ldxa [%g1 + %g5] ASI, %i7; \
restored; \
retry; nop; nop; nop; nop; \
b,a,pt %xcc, fill_fixup_dax; \
b,a,pt %xcc, fill_fixup_mna; \
b,a,pt %xcc, fill_fixup;
And the way this works is that if any of those memory accesses
generate an exception, the exception handler can revector to one of
those final three branch instructions depending upon which kind of
exception the memory access took. In this way, the fault handler
doesn't have to know if it was a spill or a fill that it's handling
the fault for. It just always branches to the last instruction in
the parent trap's handler.
For example, for a regular fault, the code goes:
winfix_trampoline:
rdpr %tpc, %g3
or %g3, 0x7c, %g3
wrpr %g3, %tnpc
done
All window trap handlers are 0x80 aligned, so if we "or" 0x7c into the
trap time program counter, we'll get that final instruction in the
trap handler.
On return from trap, we have to pull the register window in but we do
this by hand instead of just executing a "restore" instruction for
several reasons. The largest being that from Niagara and onward we
simply don't have enough levels in the trap stack to fully resolve all
possible exception cases of a window fault when we are already at
trap level 1 (which we enter to get ready to return from the original
trap).
This is executed inline via the FILL_*_RTRAP handlers. rtrap_64.S's
code branches directly to these to do the window fill by hand if
necessary. Now if you look at them, we'll see at the end:
ba,a,pt %xcc, user_rtt_fill_fixup;
ba,a,pt %xcc, user_rtt_fill_fixup;
ba,a,pt %xcc, user_rtt_fill_fixup;
And oops, all three cases are handled like a fault.
This doesn't work because each of these trap types (data access
exception, memory address unaligned, and faults) store their auxiliary
info in different registers to pass on to the C handler which does the
real work.
So in the case where the stack was unaligned, the unaligned trap
handler sets up the arg registers one way, and then we branched to
the fault handler which expects them setup another way.
So the FAULT_TYPE_* value ends up basically being garbage, and
randomly would generate the backtrace seen above.
Reported-by: Nick Alcock <nix@esperi.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-05-29 03:41:12 +00:00
|
|
|
user_rtt_fill_fixup_dax:
|
|
|
|
|
ba,pt %xcc, user_rtt_fill_fixup_common
|
|
|
|
|
mov 1, %g3
|
2006-02-04 08:10:01 +00:00
|
|
|
|
sparc64: Fix return from trap window fill crashes.
We must handle data access exception as well as memory address unaligned
exceptions from return from trap window fill faults, not just normal
TLB misses.
Otherwise we can get an OOPS that looks like this:
ld-linux.so.2(36808): Kernel bad sw trap 5 [#1]
CPU: 1 PID: 36808 Comm: ld-linux.so.2 Not tainted 4.6.0 #34
task: fff8000303be5c60 ti: fff8000301344000 task.ti: fff8000301344000
TSTATE: 0000004410001601 TPC: 0000000000a1a784 TNPC: 0000000000a1a788 Y: 00000002 Not tainted
TPC: <do_sparc64_fault+0x5c4/0x700>
g0: fff8000024fc8248 g1: 0000000000db04dc g2: 0000000000000000 g3: 0000000000000001
g4: fff8000303be5c60 g5: fff800030e672000 g6: fff8000301344000 g7: 0000000000000001
o0: 0000000000b95ee8 o1: 000000000000012b o2: 0000000000000000 o3: 0000000200b9b358
o4: 0000000000000000 o5: fff8000301344040 sp: fff80003013475c1 ret_pc: 0000000000a1a77c
RPC: <do_sparc64_fault+0x5bc/0x700>
l0: 00000000000007ff l1: 0000000000000000 l2: 000000000000005f l3: 0000000000000000
l4: fff8000301347e98 l5: fff8000024ff3060 l6: 0000000000000000 l7: 0000000000000000
i0: fff8000301347f60 i1: 0000000000102400 i2: 0000000000000000 i3: 0000000000000000
i4: 0000000000000000 i5: 0000000000000000 i6: fff80003013476a1 i7: 0000000000404d4c
I7: <user_rtt_fill_fixup+0x6c/0x7c>
Call Trace:
[0000000000404d4c] user_rtt_fill_fixup+0x6c/0x7c
The window trap handlers are slightly clever, the trap table entries for them are
composed of two pieces of code. First comes the code that actually performs
the window fill or spill trap handling, and then there are three instructions at
the end which are for exception processing.
The userland register window fill handler is:
add %sp, STACK_BIAS + 0x00, %g1; \
ldxa [%g1 + %g0] ASI, %l0; \
mov 0x08, %g2; \
mov 0x10, %g3; \
ldxa [%g1 + %g2] ASI, %l1; \
mov 0x18, %g5; \
ldxa [%g1 + %g3] ASI, %l2; \
ldxa [%g1 + %g5] ASI, %l3; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %l4; \
ldxa [%g1 + %g2] ASI, %l5; \
ldxa [%g1 + %g3] ASI, %l6; \
ldxa [%g1 + %g5] ASI, %l7; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %i0; \
ldxa [%g1 + %g2] ASI, %i1; \
ldxa [%g1 + %g3] ASI, %i2; \
ldxa [%g1 + %g5] ASI, %i3; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %i4; \
ldxa [%g1 + %g2] ASI, %i5; \
ldxa [%g1 + %g3] ASI, %i6; \
ldxa [%g1 + %g5] ASI, %i7; \
restored; \
retry; nop; nop; nop; nop; \
b,a,pt %xcc, fill_fixup_dax; \
b,a,pt %xcc, fill_fixup_mna; \
b,a,pt %xcc, fill_fixup;
And the way this works is that if any of those memory accesses
generate an exception, the exception handler can revector to one of
those final three branch instructions depending upon which kind of
exception the memory access took. In this way, the fault handler
doesn't have to know if it was a spill or a fill that it's handling
the fault for. It just always branches to the last instruction in
the parent trap's handler.
For example, for a regular fault, the code goes:
winfix_trampoline:
rdpr %tpc, %g3
or %g3, 0x7c, %g3
wrpr %g3, %tnpc
done
All window trap handlers are 0x80 aligned, so if we "or" 0x7c into the
trap time program counter, we'll get that final instruction in the
trap handler.
On return from trap, we have to pull the register window in but we do
this by hand instead of just executing a "restore" instruction for
several reasons. The largest being that from Niagara and onward we
simply don't have enough levels in the trap stack to fully resolve all
possible exception cases of a window fault when we are already at
trap level 1 (which we enter to get ready to return from the original
trap).
This is executed inline via the FILL_*_RTRAP handlers. rtrap_64.S's
code branches directly to these to do the window fill by hand if
necessary. Now if you look at them, we'll see at the end:
ba,a,pt %xcc, user_rtt_fill_fixup;
ba,a,pt %xcc, user_rtt_fill_fixup;
ba,a,pt %xcc, user_rtt_fill_fixup;
And oops, all three cases are handled like a fault.
This doesn't work because each of these trap types (data access
exception, memory address unaligned, and faults) store their auxiliary
info in different registers to pass on to the C handler which does the
real work.
So in the case where the stack was unaligned, the unaligned trap
handler sets up the arg registers one way, and then we branched to
the fault handler which expects them setup another way.
So the FAULT_TYPE_* value ends up basically being garbage, and
randomly would generate the backtrace seen above.
Reported-by: Nick Alcock <nix@esperi.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-05-29 03:41:12 +00:00
|
|
|
user_rtt_fill_fixup_mna:
|
|
|
|
|
ba,pt %xcc, user_rtt_fill_fixup_common
|
|
|
|
|
mov 2, %g3
|
2006-02-04 08:10:01 +00:00
|
|
|
|
sparc64: Fix return from trap window fill crashes.
We must handle data access exception as well as memory address unaligned
exceptions from return from trap window fill faults, not just normal
TLB misses.
Otherwise we can get an OOPS that looks like this:
ld-linux.so.2(36808): Kernel bad sw trap 5 [#1]
CPU: 1 PID: 36808 Comm: ld-linux.so.2 Not tainted 4.6.0 #34
task: fff8000303be5c60 ti: fff8000301344000 task.ti: fff8000301344000
TSTATE: 0000004410001601 TPC: 0000000000a1a784 TNPC: 0000000000a1a788 Y: 00000002 Not tainted
TPC: <do_sparc64_fault+0x5c4/0x700>
g0: fff8000024fc8248 g1: 0000000000db04dc g2: 0000000000000000 g3: 0000000000000001
g4: fff8000303be5c60 g5: fff800030e672000 g6: fff8000301344000 g7: 0000000000000001
o0: 0000000000b95ee8 o1: 000000000000012b o2: 0000000000000000 o3: 0000000200b9b358
o4: 0000000000000000 o5: fff8000301344040 sp: fff80003013475c1 ret_pc: 0000000000a1a77c
RPC: <do_sparc64_fault+0x5bc/0x700>
l0: 00000000000007ff l1: 0000000000000000 l2: 000000000000005f l3: 0000000000000000
l4: fff8000301347e98 l5: fff8000024ff3060 l6: 0000000000000000 l7: 0000000000000000
i0: fff8000301347f60 i1: 0000000000102400 i2: 0000000000000000 i3: 0000000000000000
i4: 0000000000000000 i5: 0000000000000000 i6: fff80003013476a1 i7: 0000000000404d4c
I7: <user_rtt_fill_fixup+0x6c/0x7c>
Call Trace:
[0000000000404d4c] user_rtt_fill_fixup+0x6c/0x7c
The window trap handlers are slightly clever, the trap table entries for them are
composed of two pieces of code. First comes the code that actually performs
the window fill or spill trap handling, and then there are three instructions at
the end which are for exception processing.
The userland register window fill handler is:
add %sp, STACK_BIAS + 0x00, %g1; \
ldxa [%g1 + %g0] ASI, %l0; \
mov 0x08, %g2; \
mov 0x10, %g3; \
ldxa [%g1 + %g2] ASI, %l1; \
mov 0x18, %g5; \
ldxa [%g1 + %g3] ASI, %l2; \
ldxa [%g1 + %g5] ASI, %l3; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %l4; \
ldxa [%g1 + %g2] ASI, %l5; \
ldxa [%g1 + %g3] ASI, %l6; \
ldxa [%g1 + %g5] ASI, %l7; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %i0; \
ldxa [%g1 + %g2] ASI, %i1; \
ldxa [%g1 + %g3] ASI, %i2; \
ldxa [%g1 + %g5] ASI, %i3; \
add %g1, 0x20, %g1; \
ldxa [%g1 + %g0] ASI, %i4; \
ldxa [%g1 + %g2] ASI, %i5; \
ldxa [%g1 + %g3] ASI, %i6; \
ldxa [%g1 + %g5] ASI, %i7; \
restored; \
retry; nop; nop; nop; nop; \
b,a,pt %xcc, fill_fixup_dax; \
b,a,pt %xcc, fill_fixup_mna; \
b,a,pt %xcc, fill_fixup;
And the way this works is that if any of those memory accesses
generate an exception, the exception handler can revector to one of
those final three branch instructions depending upon which kind of
exception the memory access took. In this way, the fault handler
doesn't have to know if it was a spill or a fill that it's handling
the fault for. It just always branches to the last instruction in
the parent trap's handler.
For example, for a regular fault, the code goes:
winfix_trampoline:
rdpr %tpc, %g3
or %g3, 0x7c, %g3
wrpr %g3, %tnpc
done
All window trap handlers are 0x80 aligned, so if we "or" 0x7c into the
trap time program counter, we'll get that final instruction in the
trap handler.
On return from trap, we have to pull the register window in but we do
this by hand instead of just executing a "restore" instruction for
several reasons. The largest being that from Niagara and onward we
simply don't have enough levels in the trap stack to fully resolve all
possible exception cases of a window fault when we are already at
trap level 1 (which we enter to get ready to return from the original
trap).
This is executed inline via the FILL_*_RTRAP handlers. rtrap_64.S's
code branches directly to these to do the window fill by hand if
necessary. Now if you look at them, we'll see at the end:
ba,a,pt %xcc, user_rtt_fill_fixup;
ba,a,pt %xcc, user_rtt_fill_fixup;
ba,a,pt %xcc, user_rtt_fill_fixup;
And oops, all three cases are handled like a fault.
This doesn't work because each of these trap types (data access
exception, memory address unaligned, and faults) store their auxiliary
info in different registers to pass on to the C handler which does the
real work.
So in the case where the stack was unaligned, the unaligned trap
handler sets up the arg registers one way, and then we branched to
the fault handler which expects them setup another way.
So the FAULT_TYPE_* value ends up basically being garbage, and
randomly would generate the backtrace seen above.
Reported-by: Nick Alcock <nix@esperi.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-05-29 03:41:12 +00:00
|
|
|
user_rtt_fill_fixup:
|
|
|
|
|
ba,pt %xcc, user_rtt_fill_fixup_common
|
|
|
|
|
clr %g3
|
2006-02-04 08:10:01 +00:00
|
|
|
|
|
|
|
|
user_rtt_pre_restore:
|
|
|
|
|
add %g1, 1, %g1
|
|
|
|
|
wrpr %g1, 0x0, %cwp
|
|
|
|
|
|
|
|
|
|
user_rtt_restore:
|
2005-04-16 22:20:36 +00:00
|
|
|
restore
|
|
|
|
|
rdpr %canrestore, %g1
|
|
|
|
|
wrpr %g1, 0x0, %cleanwin
|
|
|
|
|
retry
|
|
|
|
|
nop
|
|
|
|
|
|
2006-02-04 08:10:01 +00:00
|
|
|
kern_rtt: rdpr %canrestore, %g1
|
|
|
|
|
brz,pn %g1, kern_rtt_fill
|
|
|
|
|
nop
|
|
|
|
|
kern_rtt_restore:
|
2008-05-22 04:50:01 +00:00
|
|
|
stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
|
2006-02-04 08:10:01 +00:00
|
|
|
restore
|
2005-04-16 22:20:36 +00:00
|
|
|
retry
|
2006-02-04 08:10:01 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
to_kernel:
|
2019-10-15 19:18:06 +00:00
|
|
|
#ifdef CONFIG_PREEMPTION
|
2005-04-16 22:20:36 +00:00
|
|
|
ldsw [%g6 + TI_PRE_COUNT], %l5
|
|
|
|
|
brnz %l5, kern_fpucheck
|
|
|
|
|
ldx [%g6 + TI_FLAGS], %l5
|
|
|
|
|
andcc %l5, _TIF_NEED_RESCHED, %g0
|
|
|
|
|
be,pt %xcc, kern_fpucheck
|
2006-11-16 21:38:57 +00:00
|
|
|
nop
|
|
|
|
|
cmp %l4, 0
|
2005-04-16 22:20:36 +00:00
|
|
|
bne,pn %xcc, kern_fpucheck
|
2013-09-17 18:53:08 +00:00
|
|
|
nop
|
|
|
|
|
call preempt_schedule_irq
|
2005-04-16 22:20:36 +00:00
|
|
|
nop
|
|
|
|
|
ba,pt %xcc, rtrap
|
|
|
|
|
#endif
|
|
|
|
|
kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
|
|
|
|
|
brz,pt %l5, rt_continue
|
|
|
|
|
srl %l5, 1, %o0
|
|
|
|
|
add %g6, TI_FPSAVED, %l6
|
|
|
|
|
ldub [%l6 + %o0], %l2
|
|
|
|
|
sub %l5, 2, %l5
|
|
|
|
|
|
|
|
|
|
add %g6, TI_GSR, %o1
|
|
|
|
|
andcc %l2, (FPRS_FEF|FPRS_DU), %g0
|
|
|
|
|
be,pt %icc, 2f
|
|
|
|
|
and %l2, FPRS_DL, %l6
|
|
|
|
|
andcc %l2, FPRS_FEF, %g0
|
|
|
|
|
be,pn %icc, 5f
|
|
|
|
|
sll %o0, 3, %o5
|
|
|
|
|
rd %fprs, %g1
|
|
|
|
|
|
|
|
|
|
wr %g1, FPRS_FEF, %fprs
|
|
|
|
|
ldx [%o1 + %o5], %g1
|
|
|
|
|
add %g6, TI_XFSR, %o1
|
|
|
|
|
sll %o0, 8, %o2
|
|
|
|
|
add %g6, TI_FPREGS, %o3
|
|
|
|
|
brz,pn %l6, 1f
|
|
|
|
|
add %g6, TI_FPREGS+0x40, %o4
|
|
|
|
|
|
2005-10-07 20:30:49 +00:00
|
|
|
membar #Sync
|
2005-04-16 22:20:36 +00:00
|
|
|
ldda [%o3 + %o2] ASI_BLK_P, %f0
|
|
|
|
|
ldda [%o4 + %o2] ASI_BLK_P, %f16
|
2005-10-07 20:30:49 +00:00
|
|
|
membar #Sync
|
2005-04-16 22:20:36 +00:00
|
|
|
1: andcc %l2, FPRS_DU, %g0
|
|
|
|
|
be,pn %icc, 1f
|
|
|
|
|
wr %g1, 0, %gsr
|
|
|
|
|
add %o2, 0x80, %o2
|
2005-10-07 20:30:49 +00:00
|
|
|
membar #Sync
|
2005-04-16 22:20:36 +00:00
|
|
|
ldda [%o3 + %o2] ASI_BLK_P, %f32
|
|
|
|
|
ldda [%o4 + %o2] ASI_BLK_P, %f48
|
|
|
|
|
1: membar #Sync
|
|
|
|
|
ldx [%o1 + %o5], %fsr
|
|
|
|
|
2: stb %l5, [%g6 + TI_FPDEPTH]
|
|
|
|
|
ba,pt %xcc, rt_continue
|
|
|
|
|
nop
|
|
|
|
|
5: wr %g0, FPRS_FEF, %fprs
|
|
|
|
|
sll %o0, 8, %o2
|
|
|
|
|
|
|
|
|
|
add %g6, TI_FPREGS+0x80, %o3
|
|
|
|
|
add %g6, TI_FPREGS+0xc0, %o4
|
2005-10-07 20:30:49 +00:00
|
|
|
membar #Sync
|
2005-04-16 22:20:36 +00:00
|
|
|
ldda [%o3 + %o2] ASI_BLK_P, %f32
|
|
|
|
|
ldda [%o4 + %o2] ASI_BLK_P, %f48
|
|
|
|
|
membar #Sync
|
|
|
|
|
wr %g0, FPRS_DU, %fprs
|
|
|
|
|
ba,pt %xcc, rt_continue
|
|
|
|
|
stb %l5, [%g6 + TI_FPDEPTH]
|
