2009-03-03 14:06:00 +00:00
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/*
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* cimax2.c
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*
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* CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card
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*
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* Copyright (C) 2009 NetUP Inc.
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* Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
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* Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*/
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#include "cx23885.h"
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2012-10-27 14:29:23 +00:00
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#include "cimax2.h"
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2009-03-03 14:06:00 +00:00
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#include "dvb_ca_en50221.h"
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2013-11-02 09:17:47 +00:00
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/* Max transfer size done by I2C transfer functions */
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#define MAX_XFER_SIZE 64
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2009-03-03 14:06:00 +00:00
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/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
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bits 31-16
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+-----------+
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| Reserved |
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+-----------+
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bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
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+-------+-------+-------+-------+-------+-------+-------+-------+
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| WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# |
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+-------+-------+-------+-------+-------+-------+-------+-------+
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bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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+-------+-------+-------+-------+-------+-------+-------+-------+
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| DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
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+-------+-------+-------+-------+-------+-------+-------+-------+
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***/
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/* MC417 */
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#define NETUP_DATA 0x000000ff
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#define NETUP_WR 0x00008000
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#define NETUP_RD 0x00004000
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#define NETUP_ACK 0x00001000
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#define NETUP_ADHI 0x00000800
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#define NETUP_ADLO 0x00000400
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#define NETUP_CS1 0x00000200
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#define NETUP_CS0 0x00000100
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#define NETUP_EN_ALL 0x00001000
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#define NETUP_CTRL_OFF (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD)
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#define NETUP_CI_CTL 0x04
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#define NETUP_CI_RD 1
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2009-12-12 15:16:56 +00:00
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#define NETUP_IRQ_DETAM 0x1
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#define NETUP_IRQ_IRQAM 0x4
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2009-03-03 14:06:00 +00:00
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static unsigned int ci_dbg;
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module_param(ci_dbg, int, 0644);
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MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
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2010-03-06 18:46:39 +00:00
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static unsigned int ci_irq_enable;
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module_param(ci_irq_enable, int, 0644);
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MODULE_PARM_DESC(ci_irq_enable, "Enable IRQ from CAM");
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2009-03-03 14:06:00 +00:00
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#define ci_dbg_print(args...) \
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do { \
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if (ci_dbg) \
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printk(KERN_DEBUG args); \
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} while (0)
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2010-03-06 18:46:39 +00:00
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#define ci_irq_flags() (ci_irq_enable ? NETUP_IRQ_IRQAM : 0)
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2009-03-03 14:06:00 +00:00
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/* stores all private variables for communication with CI */
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struct netup_ci_state {
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struct dvb_ca_en50221 ca;
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struct mutex ca_mutex;
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struct i2c_adapter *i2c_adap;
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u8 ci_i2c_addr;
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int status;
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struct work_struct work;
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void *priv;
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2009-12-12 15:16:56 +00:00
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u8 current_irq_mode;
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int current_ci_flag;
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unsigned long next_status_checked_time;
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2009-03-03 14:06:00 +00:00
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};
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2012-10-27 14:29:23 +00:00
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static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
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2009-03-03 14:06:00 +00:00
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u8 *buf, int len)
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{
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int ret;
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struct i2c_msg msg[] = {
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{
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.addr = addr,
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.flags = 0,
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.buf = ®,
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.len = 1
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}, {
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.addr = addr,
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.flags = I2C_M_RD,
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.buf = buf,
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.len = len
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}
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};
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ret = i2c_transfer(i2c_adap, msg, 2);
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if (ret != 2) {
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ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n",
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__func__, reg, ret);
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return -1;
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}
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ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n",
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__func__, addr, reg, buf[0]);
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return 0;
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}
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2012-10-27 14:29:23 +00:00
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static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
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2009-03-03 14:06:00 +00:00
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u8 *buf, int len)
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{
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int ret;
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2013-11-02 09:17:47 +00:00
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u8 buffer[MAX_XFER_SIZE];
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2009-03-03 14:06:00 +00:00
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struct i2c_msg msg = {
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.addr = addr,
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.flags = 0,
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.buf = &buffer[0],
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.len = len + 1
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};
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2013-11-02 09:17:47 +00:00
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if (1 + len > sizeof(buffer)) {
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printk(KERN_WARNING
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"%s: i2c wr reg=%04x: len=%d is too big!\n",
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KBUILD_MODNAME, reg, len);
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return -EINVAL;
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}
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2009-03-03 14:06:00 +00:00
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buffer[0] = reg;
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memcpy(&buffer[1], buf, len);
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ret = i2c_transfer(i2c_adap, &msg, 1);
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if (ret != 1) {
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ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n",
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__func__, reg, ret);
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return -1;
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}
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return 0;
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}
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2012-10-27 14:29:23 +00:00
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static int netup_ci_get_mem(struct cx23885_dev *dev)
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2009-03-03 14:06:00 +00:00
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{
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int mem;
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unsigned long timeout = jiffies + msecs_to_jiffies(1);
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for (;;) {
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mem = cx_read(MC417_RWD);
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if ((mem & NETUP_ACK) == 0)
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break;
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if (time_after(jiffies, timeout))
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break;
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udelay(1);
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}
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cx_set(MC417_RWD, NETUP_CTRL_OFF);
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return mem & 0xff;
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}
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2012-10-27 14:29:23 +00:00
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static int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
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2009-03-17 21:13:52 +00:00
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u8 flag, u8 read, int addr, u8 data)
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2009-03-03 14:06:00 +00:00
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{
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struct netup_ci_state *state = en50221->data;
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struct cx23885_tsport *port = state->priv;
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struct cx23885_dev *dev = port->dev;
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u8 store;
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int mem;
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int ret;
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if (0 != slot)
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return -EINVAL;
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2009-12-12 15:16:56 +00:00
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if (state->current_ci_flag != flag) {
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ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
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0, &store, 1);
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if (ret != 0)
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return ret;
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2009-03-03 14:06:00 +00:00
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2009-12-12 15:16:56 +00:00
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store &= ~0x0c;
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store |= flag;
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2009-03-03 14:06:00 +00:00
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2009-12-12 15:16:56 +00:00
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ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
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0, &store, 1);
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if (ret != 0)
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return ret;
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2012-09-28 08:37:22 +00:00
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}
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2009-12-12 15:16:56 +00:00
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state->current_ci_flag = flag;
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2009-03-03 14:06:00 +00:00
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2009-09-16 16:08:06 +00:00
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mutex_lock(&dev->gpio_lock);
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2009-03-03 14:06:00 +00:00
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/* write addr */
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cx_write(MC417_OEN, NETUP_EN_ALL);
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cx_write(MC417_RWD, NETUP_CTRL_OFF |
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NETUP_ADLO | (0xff & addr));
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cx_clear(MC417_RWD, NETUP_ADLO);
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cx_write(MC417_RWD, NETUP_CTRL_OFF |
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NETUP_ADHI | (0xff & (addr >> 8)));
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cx_clear(MC417_RWD, NETUP_ADHI);
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2009-09-16 16:08:06 +00:00
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if (read) { /* data in */
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2009-03-03 14:06:00 +00:00
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cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA);
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2009-09-16 16:08:06 +00:00
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} else /* data out */
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2009-03-03 14:06:00 +00:00
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cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
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/* choose chip */
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cx_clear(MC417_RWD,
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(state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1);
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/* read/write */
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cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR);
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mem = netup_ci_get_mem(dev);
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2009-09-16 16:08:06 +00:00
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mutex_unlock(&dev->gpio_lock);
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2009-03-03 14:06:00 +00:00
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if (!read)
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if (mem < 0)
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return -EREMOTEIO;
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2009-12-12 15:16:56 +00:00
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ci_dbg_print("%s: %s: chipaddr=[0x%x] addr=[0x%02x], %s=%x\n", __func__,
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(read) ? "read" : "write", state->ci_i2c_addr, addr,
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2009-03-03 14:06:00 +00:00
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(flag == NETUP_CI_CTL) ? "ctl" : "mem",
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(read) ? mem : data);
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if (read)
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return mem;
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return 0;
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}
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int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
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int slot, int addr)
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{
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return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0);
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}
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int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
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int slot, int addr, u8 data)
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{
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return netup_ci_op_cam(en50221, slot, 0, 0, addr, data);
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}
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2012-10-27 14:29:23 +00:00
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int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
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u8 addr)
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2009-03-03 14:06:00 +00:00
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{
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return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL,
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NETUP_CI_RD, addr, 0);
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}
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int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
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u8 addr, u8 data)
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{
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return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data);
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}
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int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
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{
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struct netup_ci_state *state = en50221->data;
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u8 buf = 0x80;
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int ret;
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if (0 != slot)
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return -EINVAL;
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udelay(500);
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ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
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0, &buf, 1);
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if (ret != 0)
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return ret;
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udelay(500);
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buf = 0x00;
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ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
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0, &buf, 1);
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msleep(1000);
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dvb_ca_en50221_camready_irq(&state->ca, 0);
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return 0;
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}
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int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
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{
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/* not implemented */
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return 0;
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}
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2012-10-27 14:29:23 +00:00
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static int netup_ci_set_irq(struct dvb_ca_en50221 *en50221, u8 irq_mode)
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2009-12-12 15:16:56 +00:00
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{
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struct netup_ci_state *state = en50221->data;
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int ret;
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if (irq_mode == state->current_irq_mode)
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return 0;
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ci_dbg_print("%s: chipaddr=[0x%x] setting ci IRQ to [0x%x] \n",
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__func__, state->ci_i2c_addr, irq_mode);
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ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
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0x1b, &irq_mode, 1);
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if (ret != 0)
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return ret;
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state->current_irq_mode = irq_mode;
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return 0;
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}
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2009-03-03 14:06:00 +00:00
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int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
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{
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struct netup_ci_state *state = en50221->data;
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2009-12-12 15:16:56 +00:00
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u8 buf;
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2009-03-03 14:06:00 +00:00
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if (0 != slot)
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return -EINVAL;
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2009-12-12 15:16:56 +00:00
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|
|
netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
|
|
|
|
0, &buf, 1);
|
|
|
|
buf |= 0x60;
|
|
|
|
|
2009-03-03 14:06:00 +00:00
|
|
|
return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
|
|
|
|
0, &buf, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* work handler */
|
|
|
|
static void netup_read_ci_status(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct netup_ci_state *state =
|
|
|
|
container_of(work, struct netup_ci_state, work);
|
|
|
|
u8 buf[33];
|
|
|
|
int ret;
|
|
|
|
|
2009-12-12 15:16:56 +00:00
|
|
|
/* CAM module IRQ processing. fast operation */
|
|
|
|
dvb_ca_en50221_frda_irq(&state->ca, 0);
|
2009-03-03 14:06:00 +00:00
|
|
|
|
2009-12-12 15:16:56 +00:00
|
|
|
/* CAM module INSERT/REMOVE processing. slow operation because of i2c
|
|
|
|
* transfers */
|
|
|
|
if (time_after(jiffies, state->next_status_checked_time)
|
|
|
|
|| !state->status) {
|
|
|
|
ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
|
|
|
|
0, &buf[0], 33);
|
|
|
|
|
|
|
|
state->next_status_checked_time = jiffies
|
|
|
|
+ msecs_to_jiffies(1000);
|
|
|
|
|
|
|
|
if (ret != 0)
|
|
|
|
return;
|
2009-03-03 14:06:00 +00:00
|
|
|
|
2009-12-12 15:16:56 +00:00
|
|
|
ci_dbg_print("%s: Slot Status Addr=[0x%04x], "
|
|
|
|
"Reg=[0x%02x], data=%02x, "
|
|
|
|
"TS config = %02x\n", __func__,
|
|
|
|
state->ci_i2c_addr, 0, buf[0],
|
|
|
|
buf[0]);
|
2009-03-03 14:06:00 +00:00
|
|
|
|
2009-12-12 15:16:56 +00:00
|
|
|
|
|
|
|
if (buf[0] & 1)
|
|
|
|
state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
|
|
|
|
DVB_CA_EN50221_POLL_CAM_READY;
|
|
|
|
else
|
|
|
|
state->status = 0;
|
2010-12-31 05:04:38 +00:00
|
|
|
}
|
2009-03-03 14:06:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* CI irq handler */
|
|
|
|
int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status)
|
|
|
|
{
|
|
|
|
struct cx23885_tsport *port = NULL;
|
|
|
|
struct netup_ci_state *state = NULL;
|
|
|
|
|
2010-12-31 05:04:38 +00:00
|
|
|
ci_dbg_print("%s:\n", __func__);
|
|
|
|
|
|
|
|
if (0 == (pci_status & (PCI_MSK_GPIO0 | PCI_MSK_GPIO1)))
|
2009-03-03 14:06:00 +00:00
|
|
|
return 0;
|
|
|
|
|
2010-12-31 05:04:38 +00:00
|
|
|
if (pci_status & PCI_MSK_GPIO0) {
|
|
|
|
port = &dev->ts1;
|
|
|
|
state = port->port_priv;
|
|
|
|
schedule_work(&state->work);
|
|
|
|
ci_dbg_print("%s: Wakeup CI0\n", __func__);
|
|
|
|
}
|
2009-03-03 14:06:00 +00:00
|
|
|
|
2010-12-31 05:04:38 +00:00
|
|
|
if (pci_status & PCI_MSK_GPIO1) {
|
|
|
|
port = &dev->ts2;
|
|
|
|
state = port->port_priv;
|
|
|
|
schedule_work(&state->work);
|
|
|
|
ci_dbg_print("%s: Wakeup CI1\n", __func__);
|
|
|
|
}
|
2009-03-03 14:06:00 +00:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2012-10-27 14:29:23 +00:00
|
|
|
int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
|
|
|
|
int slot, int open)
|
2009-03-03 14:06:00 +00:00
|
|
|
{
|
|
|
|
struct netup_ci_state *state = en50221->data;
|
|
|
|
|
|
|
|
if (0 != slot)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2010-03-06 18:46:39 +00:00
|
|
|
netup_ci_set_irq(en50221, open ? (NETUP_IRQ_DETAM | ci_irq_flags())
|
2009-12-12 15:16:56 +00:00
|
|
|
: NETUP_IRQ_DETAM);
|
|
|
|
|
2009-03-03 14:06:00 +00:00
|
|
|
return state->status;
|
|
|
|
}
|
|
|
|
|
|
|
|
int netup_ci_init(struct cx23885_tsport *port)
|
|
|
|
{
|
|
|
|
struct netup_ci_state *state;
|
|
|
|
u8 cimax_init[34] = {
|
|
|
|
0x00, /* module A control*/
|
|
|
|
0x00, /* auto select mask high A */
|
|
|
|
0x00, /* auto select mask low A */
|
|
|
|
0x00, /* auto select pattern high A */
|
|
|
|
0x00, /* auto select pattern low A */
|
|
|
|
0x44, /* memory access time A */
|
|
|
|
0x00, /* invert input A */
|
|
|
|
0x00, /* RFU */
|
|
|
|
0x00, /* RFU */
|
|
|
|
0x00, /* module B control*/
|
|
|
|
0x00, /* auto select mask high B */
|
|
|
|
0x00, /* auto select mask low B */
|
|
|
|
0x00, /* auto select pattern high B */
|
|
|
|
0x00, /* auto select pattern low B */
|
|
|
|
0x44, /* memory access time B */
|
|
|
|
0x00, /* invert input B */
|
|
|
|
0x00, /* RFU */
|
|
|
|
0x00, /* RFU */
|
|
|
|
0x00, /* auto select mask high Ext */
|
|
|
|
0x00, /* auto select mask low Ext */
|
|
|
|
0x00, /* auto select pattern high Ext */
|
|
|
|
0x00, /* auto select pattern low Ext */
|
|
|
|
0x00, /* RFU */
|
|
|
|
0x02, /* destination - module A */
|
|
|
|
0x01, /* power on (use it like store place) */
|
|
|
|
0x00, /* RFU */
|
|
|
|
0x00, /* int status read only */
|
2010-03-06 18:46:39 +00:00
|
|
|
ci_irq_flags() | NETUP_IRQ_DETAM, /* DETAM, IRQAM unmasked */
|
2009-12-12 15:16:56 +00:00
|
|
|
0x05, /* EXTINT=active-high, INT=push-pull */
|
2009-03-03 14:06:00 +00:00
|
|
|
0x00, /* USCG1 */
|
|
|
|
0x04, /* ack active low */
|
|
|
|
0x00, /* LOCK = 0 */
|
|
|
|
0x33, /* serial mode, rising in, rising out, MSB first*/
|
2011-03-31 01:57:33 +00:00
|
|
|
0x31, /* synchronization */
|
2009-03-03 14:06:00 +00:00
|
|
|
};
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ci_dbg_print("%s\n", __func__);
|
|
|
|
state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL);
|
|
|
|
if (!state) {
|
|
|
|
ci_dbg_print("%s: Unable create CI structure!\n", __func__);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
port->port_priv = state;
|
|
|
|
|
|
|
|
switch (port->nr) {
|
|
|
|
case 1:
|
|
|
|
state->ci_i2c_addr = 0x40;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
state->ci_i2c_addr = 0x41;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap;
|
|
|
|
state->ca.owner = THIS_MODULE;
|
|
|
|
state->ca.read_attribute_mem = netup_ci_read_attribute_mem;
|
|
|
|
state->ca.write_attribute_mem = netup_ci_write_attribute_mem;
|
|
|
|
state->ca.read_cam_control = netup_ci_read_cam_ctl;
|
|
|
|
state->ca.write_cam_control = netup_ci_write_cam_ctl;
|
|
|
|
state->ca.slot_reset = netup_ci_slot_reset;
|
|
|
|
state->ca.slot_shutdown = netup_ci_slot_shutdown;
|
|
|
|
state->ca.slot_ts_enable = netup_ci_slot_ts_ctl;
|
|
|
|
state->ca.poll_slot_status = netup_poll_ci_slot_status;
|
|
|
|
state->ca.data = state;
|
|
|
|
state->priv = port;
|
2010-03-06 18:46:39 +00:00
|
|
|
state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM;
|
2009-03-03 14:06:00 +00:00
|
|
|
|
|
|
|
ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
|
|
|
|
0, &cimax_init[0], 34);
|
|
|
|
/* lock registers */
|
|
|
|
ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
|
|
|
|
0x1f, &cimax_init[0x18], 1);
|
|
|
|
/* power on slots */
|
|
|
|
ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
|
|
|
|
0x18, &cimax_init[0x18], 1);
|
|
|
|
|
|
|
|
if (0 != ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = dvb_ca_en50221_init(&port->frontends.adapter,
|
|
|
|
&state->ca,
|
|
|
|
/* flags */ 0,
|
|
|
|
/* n_slots */ 1);
|
|
|
|
if (0 != ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
INIT_WORK(&state->work, netup_read_ci_status);
|
2009-07-20 15:27:27 +00:00
|
|
|
schedule_work(&state->work);
|
2009-03-03 14:06:00 +00:00
|
|
|
|
|
|
|
ci_dbg_print("%s: CI initialized!\n", __func__);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
|
|
|
|
kfree(state);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void netup_ci_exit(struct cx23885_tsport *port)
|
|
|
|
{
|
|
|
|
struct netup_ci_state *state;
|
|
|
|
|
|
|
|
if (NULL == port)
|
|
|
|
return;
|
|
|
|
|
|
|
|
state = (struct netup_ci_state *)port->port_priv;
|
|
|
|
if (NULL == state)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (NULL == state->ca.data)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dvb_ca_en50221_release(&state->ca);
|
|
|
|
kfree(state);
|
|
|
|
}
|