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linux/drivers/mtd/spi-nor/Kconfig

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mtd: spi-nor: allow to be built as module There's no reason this can't be a module. Also, give SPI-NOR its own submenu. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-10 18:05:34 +00:00
menuconfig MTD_SPI_NOR
tristate "SPI-NOR device support"
mtd: spi-nor: add the framework for SPI NOR This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased to include additional m25p_ids[] entry] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-02-24 10:37:37 +00:00
depends on MTD
help
This is the framework for the SPI NOR which can be used by the SPI
device drivers and the SPI-NOR device driver.
mtd: spi-nor: shorten Kconfig naming Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-09 03:30:25 +00:00
if MTD_SPI_NOR
mtd: mtk-nor: new Mediatek serial flash controller driver Add spi nor flash driver for mediatek controller Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-11-18 03:30:02 +00:00
config MTD_MT81xx_NOR
tristate "Mediatek MT81xx SPI NOR flash controller"
mtd: Fix dependencies for !HAS_IOMEM archs Not every arch has io memory. So, unbreak the build by fixing the dependencies. Signed-off-by: Richard Weinberger <richard@nod.at> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-25 22:24:10 +00:00
depends on HAS_IOMEM
mtd: mtk-nor: new Mediatek serial flash controller driver Add spi nor flash driver for mediatek controller Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-11-18 03:30:02 +00:00
help
This enables access to SPI NOR flash, using MT81xx SPI NOR flash
controller. This controller does not support generic SPI BUS, it only
supports SPI NOR Flash.
mtd: spi-nor: add Kconfig option to disable 4K sectors Current situation with 4K sectors is quite messy. First of all, some MTD "users" don't work with such small size. An example may be UBIFS which requires 15 KiB erase blocks as a minimum. In theory spi-nor should provide multiple erase regions and MTD "users" should use the one they need. Unforunately that is not implemented. In the result our flashes database in spi-nor is hackish. For some flashes we pretend they don't support 4K sectors just because some distribution uses UBIFS on it. This ofc leads to conflicts, like Samsung using w25q128 with 4K sectors vs. OpenWrt requiring it to pretend it's 64 KiB blocks only. My idea (plan?) for fixing this situation: 1) Use real hw info (this requires a way for disabling 4K for now) 2) Provide detailed info about erase regions 3) Make UBIFS work with devices that support 4K sectors Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-08-17 09:27:26 +00:00
config MTD_SPI_NOR_USE_4K_SECTORS
bool "Use small 4096 B erase sectors"
default y
help
Many flash memories support erasing small (4096 B) sectors. Depending
on the usage this feature may provide performance gain in comparison
to erasing whole blocks (32/64 KiB).
Changing a small part of the flash's contents is usually faster with
small sectors. On the other hand erasing should be faster when using
64 KiB block instead of 16 × 4 KiB sectors.
Please note that some tools/drivers/filesystems may not work with
4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
mtd: spi-nor: add memory controllers for the Aspeed AST2500 SoC This driver adds mtd support for the Aspeed AST2500 SoC static memory controllers : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver * SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . supports SPI type flash memory Each controller has a memory range on which it maps its flash module slaves. Each slave is assigned a memory window for its mapping that can be changed at bootime with the Segment Address Register. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Currently, only the User mode is supported. Command mode needs a little more work to check that the memory window on the AHB bus fits the module size. Based on previous work from Milton D. Miller II <miltonm@us.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2016-12-21 16:57:17 +00:00
config SPI_ASPEED_SMC
tristate "Aspeed flash controllers in SPI mode"
depends on ARCH_ASPEED || COMPILE_TEST
depends on HAS_IOMEM && OF
help
This enables support for the Firmware Memory controller (FMC)
mtd: aspeed: add memory controllers for the Aspeed AST2400 SoC This driver adds mtd support for the Aspeed AST2400 SoC static memory controllers: * New Static Memory Controller (referred as FMC) . BMC firmware . AST2500 compatible register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. * SPI Flash Controller (SPI) . host Firmware . slightly different register set, between AST2500 and the legacy controller . supports SPI flash memory . 1 chip select pin (CE0) The legacy static memory controller (referred as SMC) is not supported, as well as types other than SPI. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2016-12-21 16:57:18 +00:00
in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
mtd: spi-nor: add memory controllers for the Aspeed AST2500 SoC This driver adds mtd support for the Aspeed AST2500 SoC static memory controllers : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver * SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . supports SPI type flash memory Each controller has a memory range on which it maps its flash module slaves. Each slave is assigned a memory window for its mapping that can be changed at bootime with the Segment Address Register. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Currently, only the User mode is supported. Command mode needs a little more work to check that the memory window on the AHB bus fits the module size. Based on previous work from Milton D. Miller II <miltonm@us.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2016-12-21 16:57:17 +00:00
and support for the SPI flash memory controller (SPI) for
the host firmware. The implementation only supports SPI NOR.
mtd: atmel-quadspi: add driver for Atmel QSPI controller This driver add support to the new Atmel QSPI controller embedded into sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI controller. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-13 15:10:26 +00:00
config SPI_ATMEL_QUADSPI
tristate "Atmel Quad SPI Controller"
depends on ARCH_AT91 || (ARM && COMPILE_TEST)
depends on OF && HAS_IOMEM
help
This enables support for the Quad SPI controller in master mode.
This driver does not support generic SPI. The implementation only
supports SPI NOR.
mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller Add support for the Cadence QSPI controller. This controller is present in the Altera SoCFPGA SoCs and this driver has been tested on the Cyclone V SoC. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-04 00:39:34 +00:00
config SPI_CADENCE_QUADSPI
tristate "Cadence Quad SPI controller"
mtd: spi-nor: Allow Cadence QSPI support for ARM64 Allow ARM64 support for the Cadence QSPI interface by adding ARM64 as a dependency. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
2017-09-29 16:07:49 +00:00
depends on OF && (ARM || ARM64 || COMPILE_TEST)
mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller Add support for the Cadence QSPI controller. This controller is present in the Altera SoCFPGA SoCs and this driver has been tested on the Cyclone V SoC. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-04 00:39:34 +00:00
help
Enable support for the Cadence Quad SPI Flash controller.
Cadence QSPI is a specialized controller for connecting an SPI
Flash over 1/2/4-bit wide bus. Enable this option if you have a
device with a Cadence QSPI controller and want to access the
Flash as an MTD device.
mtd: spi-nor: Add Freescale QuadSPI driver (0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-02-24 10:37:42 +00:00
config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
mtd: spi-nor: fsl-quadspi: add support for layerscape LS1043a and LS2080A in the Layerscape family also support Freescale Quad SPI, make Quad SPI selectable for these hardwares. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-26 07:23:57 +00:00
depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
mtd: fsl-quadspi: allow building for other ARCHes with COMPILE_TEST This driver doesn't actually need ARCH_MXC to compile. Relax the constraints. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Han xu <han.xu@freescale.com>
2015-10-12 20:35:16 +00:00
depends on HAS_IOMEM
mtd: spi-nor: Add Freescale QuadSPI driver (0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-02-24 10:37:42 +00:00
help
This enables support for the Quad SPI controller in master mode.
mtd: spi-nor: Improve Kconfig help text for SPI_FSL_QUADSPI The current "We only connect the NOR to this controller now." text is not very clear, so explain it better by saying that generic SPI is not supported by SPI_FSL_QUADSPI and only SPI NOR is. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-08-13 17:02:05 +00:00
This controller does not support generic SPI. It only supports
SPI NOR.
mtd: spi-nor: shorten Kconfig naming Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-09 03:30:25 +00:00
mtd: spi-nor: add hisilicon spi-nor flash controller driver Add hisilicon spi-nor flash controller driver Signed-off-by: Binquan Peng <pengbinquan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-28 07:48:19 +00:00
config SPI_HISI_SFC
tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
depends on ARCH_HISI || COMPILE_TEST
depends on HAS_IOMEM && HAS_DMA
help
This enables support for hisilicon SPI-NOR flash controller.
mtd: spi-nor: add driver for NXP SPI Flash Interface (SPIFI) Add SPI-NOR driver for the SPI Flash Interface (SPIFI) controller that is found on newer NXP MCU devices. The controller supports serial SPI Flash devices with 1-, 2- and 4-bit width in either SPI mode 0 or 3. The controller can operate in either command or memory mode. In memory mode the Flash is exposed as normal memory and can be directly accessed by the CPU. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-08-13 17:19:40 +00:00
config SPI_NXP_SPIFI
tristate "NXP SPI Flash Interface (SPIFI)"
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
depends on HAS_IOMEM
help
Enable support for the NXP LPC SPI Flash Interface controller.
SPIFI is a specialized controller for connecting serial SPI
Flash. Enable this option if you have a device with a SPIFI
controller and want to access the Flash as a mtd device.
spi-nor: Add support for Intel SPI serial flash controller Add support for the SPI serial flash host controller found on many Intel CPUs including Baytrail and Braswell. The SPI serial flash controller is used to access BIOS and other platform specific information. By default the driver exposes a single read-only MTD device but with a module parameter "writeable=1" the MTD device can be made read-write which makes it possible to upgrade BIOS directly from Linux. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-28 12:06:24 +00:00
config SPI_INTEL_SPI
tristate
mtd: spi-nor: intel-spi: Add support for Intel Denverton SPI serial flash controller Intel Denverton exposes the SPI serial flash controller as a PCI device instead of being part of the LPC chip as previous generations did. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
2017-06-29 11:45:42 +00:00
config SPI_INTEL_SPI_PCI
mtd: spi-nor: intel-spi: Explicitly mark the driver as dangerous in Kconfig The driver is not meant for normal users at all but instead such users who really know what they are doing and are able to build their own kernel to enable it. Mark both driver Kconfig entries as dangerous to make sure the driver is not accidentally enabled without understanding possible consequences in doing so. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-02-05 11:33:00 +00:00
tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)"
mtd: spi-nor: intel-spi: Add support for Intel Denverton SPI serial flash controller Intel Denverton exposes the SPI serial flash controller as a PCI device instead of being part of the LPC chip as previous generations did. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
2017-06-29 11:45:42 +00:00
depends on X86 && PCI
select SPI_INTEL_SPI
help
This enables PCI support for the Intel PCH/PCU SPI controller in
master mode. This controller is present in modern Intel hardware
and is used to hold BIOS and other persistent settings. Using
this driver it is possible to upgrade BIOS directly from Linux.
Say N here unless you know what you are doing. Overwriting the
SPI flash may render the system unbootable.
To compile this driver as a module, choose M here: the module
will be called intel-spi-pci.
spi-nor: Add support for Intel SPI serial flash controller Add support for the SPI serial flash host controller found on many Intel CPUs including Baytrail and Braswell. The SPI serial flash controller is used to access BIOS and other platform specific information. By default the driver exposes a single read-only MTD device but with a module parameter "writeable=1" the MTD device can be made read-write which makes it possible to upgrade BIOS directly from Linux. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-28 12:06:24 +00:00
config SPI_INTEL_SPI_PLATFORM
mtd: spi-nor: intel-spi: Explicitly mark the driver as dangerous in Kconfig The driver is not meant for normal users at all but instead such users who really know what they are doing and are able to build their own kernel to enable it. Mark both driver Kconfig entries as dangerous to make sure the driver is not accidentally enabled without understanding possible consequences in doing so. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-02-05 11:33:00 +00:00
tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"
spi-nor: Add support for Intel SPI serial flash controller Add support for the SPI serial flash host controller found on many Intel CPUs including Baytrail and Braswell. The SPI serial flash controller is used to access BIOS and other platform specific information. By default the driver exposes a single read-only MTD device but with a module parameter "writeable=1" the MTD device can be made read-write which makes it possible to upgrade BIOS directly from Linux. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-28 12:06:24 +00:00
depends on X86
select SPI_INTEL_SPI
help
This enables platform support for the Intel PCH/PCU SPI
controller in master mode. This controller is present in modern
Intel hardware and is used to hold BIOS and other persistent
settings. Using this driver it is possible to upgrade BIOS
directly from Linux.
Say N here unless you know what you are doing. Overwriting the
SPI flash may render the system unbootable.
To compile this driver as a module, choose M here: the module
will be called intel-spi-platform.
mtd: spi-nor: add driver for STM32 quad spi flash controller The quadspi is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-04-13 17:15:57 +00:00
config SPI_STM32_QUADSPI
tristate "STM32 Quad SPI controller"
mtd: spi-nor: stm32-quadspi: allow building with COMPILE_TEST Cc: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
2017-05-02 01:13:00 +00:00
depends on ARCH_STM32 || COMPILE_TEST
mtd: spi-nor: add driver for STM32 quad spi flash controller The quadspi is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-04-13 17:15:57 +00:00
help
This enables support for the STM32 Quad SPI controller.
We only connect the NOR to this controller.
mtd: spi-nor: shorten Kconfig naming Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-09 03:30:25 +00:00
endif # MTD_SPI_NOR
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