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41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
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GPIO controllers on MPC8xxx SoCs
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This is for the non-QE/CPM/GUTs GPIO controllers as found on
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8349, 8572, 8610 and compatible.
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Every GPIO controller node must have #gpio-cells property defined,
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this information will be used to translate gpio-specifiers.
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Required properties:
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- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
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83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters (currently unused).
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- interrupts : Interrupt mapping for GPIO IRQ (currently unused).
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- interrupt-parent : Phandle for the interrupt controller that
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services interrupts for this device.
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- gpio-controller : Marks the port as GPIO controller.
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Example of gpio-controller nodes for a MPC8347 SoC:
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gpio1: gpio-controller@c00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
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reg = <0xc00 0x100>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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gpio2: gpio-controller@d00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
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reg = <0xd00 0x100>;
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interrupts = <75 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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See booting-without-of.txt for details of how to specify GPIO
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information for devices.
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