2010-04-15 22:11:37 +00:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#ifndef __ASM_KVM_BOOK3S_64_H__
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#define __ASM_KVM_BOOK3S_64_H__
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2013-10-07 16:47:51 +00:00
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#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
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2011-12-09 13:44:13 +00:00
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static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
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2010-04-15 22:11:37 +00:00
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{
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2011-12-09 13:44:13 +00:00
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preempt_disable();
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2010-04-15 22:11:37 +00:00
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return &get_paca()->shadow_vcpu;
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}
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2011-12-09 13:44:13 +00:00
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static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
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{
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preempt_enable();
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}
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#endif
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2010-04-15 22:11:37 +00:00
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2011-06-29 00:22:41 +00:00
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#define SPAPR_TCE_SHIFT 12
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2013-10-07 16:47:52 +00:00
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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KVM: PPC: Book3S HV: Make the guest hash table size configurable
This adds a new ioctl to enable userspace to control the size of the guest
hashed page table (HPT) and to clear it out when resetting the guest.
The KVM_PPC_ALLOCATE_HTAB ioctl is a VM ioctl and takes as its parameter
a pointer to a u32 containing the desired order of the HPT (log base 2
of the size in bytes), which is updated on successful return to the
actual order of the HPT which was allocated.
There must be no vcpus running at the time of this ioctl. To enforce
this, we now keep a count of the number of vcpus running in
kvm->arch.vcpus_running.
If the ioctl is called when a HPT has already been allocated, we don't
reallocate the HPT but just clear it out. We first clear the
kvm->arch.rma_setup_done flag, which has two effects: (a) since we hold
the kvm->lock mutex, it will prevent any vcpus from starting to run until
we're done, and (b) it means that the first vcpu to run after we're done
will re-establish the VRMA if necessary.
If userspace doesn't call this ioctl before running the first vcpu, the
kernel will allocate a default-sized HPT at that point. We do it then
rather than when creating the VM, as the code did previously, so that
userspace has a chance to do the ioctl if it wants.
When allocating the HPT, we can allocate either from the kernel page
allocator, or from the preallocated pool. If userspace is asking for
a different size from the preallocated HPTs, we first try to allocate
using the kernel page allocator. Then we try to allocate from the
preallocated pool, and then if that fails, we try allocating decreasing
sizes from the kernel page allocator, down to the minimum size allowed
(256kB). Note that the kernel page allocator limits allocations to
1 << CONFIG_FORCE_MAX_ZONEORDER pages, which by default corresponds to
16MB (on 64-bit powerpc, at least).
Signed-off-by: Paul Mackerras <paulus@samba.org>
[agraf: fix module compilation]
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-05-04 02:32:53 +00:00
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#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
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2011-12-12 12:27:39 +00:00
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#endif
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KVM: PPC: Implement MMIO emulation support for Book3S HV guests
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page. An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.
When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.
This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:36:37 +00:00
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#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
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2011-12-12 12:30:16 +00:00
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/*
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* We use a lock bit in HPTE dword 0 to synchronize updates and
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* accesses to each HPTE, and another bit to indicate non-present
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* HPTEs.
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*/
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#define HPTE_V_HVLOCK 0x40UL
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KVM: PPC: Implement MMIO emulation support for Book3S HV guests
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page. An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.
When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.
This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:36:37 +00:00
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#define HPTE_V_ABSENT 0x20UL
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2011-12-12 12:30:16 +00:00
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2012-11-19 22:52:49 +00:00
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/*
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* We use this bit in the guest_rpte field of the revmap entry
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* to indicate a modified HPTE.
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*/
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#define HPTE_GR_MODIFIED (1ul << 62)
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/* These bits are reserved in the guest view of the HPTE */
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#define HPTE_GR_RESERVED HPTE_GR_MODIFIED
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2014-06-11 08:16:06 +00:00
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static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
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2011-12-12 12:30:16 +00:00
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{
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unsigned long tmp, old;
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2014-06-11 08:16:06 +00:00
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__be64 be_lockbit, be_bits;
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/*
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* We load/store in native endian, but the HTAB is in big endian. If
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* we byte swap all data we apply on the PTE we're implicitly correct
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* again.
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*/
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be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
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be_bits = cpu_to_be64(bits);
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2011-12-12 12:30:16 +00:00
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asm volatile(" ldarx %0,0,%2\n"
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" and. %1,%0,%3\n"
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" bne 2f\n"
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2014-06-11 08:16:06 +00:00
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" or %0,%0,%4\n"
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2011-12-12 12:30:16 +00:00
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" stdcx. %0,0,%2\n"
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" beq+ 2f\n"
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2012-10-15 01:20:50 +00:00
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" mr %1,%3\n"
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2011-12-12 12:30:16 +00:00
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"2: isync"
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: "=&r" (tmp), "=&r" (old)
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2014-06-11 08:16:06 +00:00
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: "r" (hpte), "r" (be_bits), "r" (be_lockbit)
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2011-12-12 12:30:16 +00:00
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: "cc", "memory");
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return old == 0;
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}
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KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
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static inline int __hpte_actual_psize(unsigned int lp, int psize)
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{
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int i, shift;
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unsigned int mask;
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/* start from 1 ignoring MMU_PAGE_4K */
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for (i = 1; i < MMU_PAGE_COUNT; i++) {
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/* invalid penc */
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if (mmu_psize_defs[psize].penc[i] == -1)
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continue;
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/*
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* encoding bits per actual page size
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* PTE LP actual page size
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* rrrr rrrz >=8KB
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* rrrr rrzz >=16KB
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* rrrr rzzz >=32KB
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* rrrr zzzz >=64KB
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* .......
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*/
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shift = mmu_psize_defs[i].shift - LP_SHIFT;
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if (shift > LP_BITS)
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shift = LP_BITS;
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mask = (1 << shift) - 1;
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if ((lp & mask) == mmu_psize_defs[psize].penc[i])
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return i;
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}
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return -1;
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}
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2011-11-08 07:08:52 +00:00
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static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
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unsigned long pte_index)
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{
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2014-06-11 15:13:55 +00:00
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int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
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KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
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unsigned int penc;
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unsigned long rb = 0, va_low, sllp;
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unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
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2014-06-11 15:13:55 +00:00
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if (v & HPTE_V_LARGE) {
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KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
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for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) {
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/* valid entries have a shift value */
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if (!mmu_psize_defs[b_psize].shift)
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continue;
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2011-11-08 07:08:52 +00:00
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|
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|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
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|
a_psize = __hpte_actual_psize(lp, b_psize);
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if (a_psize != -1)
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break;
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}
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}
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/*
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* Ignore the top 14 bits of va
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* v have top two bits covering segment size, hence move
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* by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
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* AVA field in v also have the lower 23 bits ignored.
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* For base page size 4K we need 14 .. 65 bits (so need to
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* collect extra 11 bits)
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|
* For others we need 14..14+i
|
|
|
|
|
*/
|
|
|
|
|
/* This covers 14..54 bits of va*/
|
2011-11-08 07:08:52 +00:00
|
|
|
rb = (v & ~0x7fUL) << 16; /* AVA field */
|
2014-06-29 11:17:30 +00:00
|
|
|
|
2014-11-03 04:51:56 +00:00
|
|
|
rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
/*
|
|
|
|
|
* AVA in v had cleared lower 23 bits. We need to derive
|
|
|
|
|
* that from pteg index
|
|
|
|
|
*/
|
2011-11-08 07:08:52 +00:00
|
|
|
va_low = pte_index >> 3;
|
|
|
|
|
if (v & HPTE_V_SECONDARY)
|
|
|
|
|
va_low = ~va_low;
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
/*
|
|
|
|
|
* get the vpn bits from va_low using reverse of hashing.
|
|
|
|
|
* In v we have va with 23 bits dropped and then left shifted
|
|
|
|
|
* HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
|
|
|
|
|
* right shift it with (SID_SHIFT - (23 - 7))
|
|
|
|
|
*/
|
2011-11-08 07:08:52 +00:00
|
|
|
if (!(v & HPTE_V_1TB_SEG))
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
va_low ^= v >> (SID_SHIFT - 16);
|
2011-11-08 07:08:52 +00:00
|
|
|
else
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
va_low ^= v >> (SID_SHIFT_1T - 16);
|
2011-11-08 07:08:52 +00:00
|
|
|
va_low &= 0x7ff;
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
|
|
|
|
|
switch (b_psize) {
|
|
|
|
|
case MMU_PAGE_4K:
|
|
|
|
|
sllp = ((mmu_psize_defs[a_psize].sllp & SLB_VSID_L) >> 6) |
|
|
|
|
|
((mmu_psize_defs[a_psize].sllp & SLB_VSID_LP) >> 4);
|
|
|
|
|
rb |= sllp << 5; /* AP field */
|
|
|
|
|
rb |= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
{
|
|
|
|
|
int aval_shift;
|
|
|
|
|
/*
|
2014-06-29 11:17:30 +00:00
|
|
|
* remaining bits of AVA/LP fields
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
* Also contain the rr bits of LP
|
|
|
|
|
*/
|
2014-06-29 11:17:30 +00:00
|
|
|
rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
/*
|
|
|
|
|
* Now clear not needed LP bits based on actual psize
|
|
|
|
|
*/
|
|
|
|
|
rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
|
|
|
|
|
/*
|
|
|
|
|
* AVAL field 58..77 - base_page_shift bits of va
|
|
|
|
|
* we have space for 58..64 bits, Missing bits should
|
|
|
|
|
* be zero filled. +1 is to take care of L bit shift
|
|
|
|
|
*/
|
|
|
|
|
aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;
|
|
|
|
|
rb |= ((va_low << aval_shift) & 0xfe);
|
|
|
|
|
|
|
|
|
|
rb |= 1; /* L field */
|
|
|
|
|
penc = mmu_psize_defs[b_psize].penc[a_psize];
|
|
|
|
|
rb |= penc << 12; /* LP field */
|
|
|
|
|
break;
|
|
|
|
|
}
|
2011-11-08 07:08:52 +00:00
|
|
|
}
|
|
|
|
|
rb |= (v >> 54) & 0x300; /* B field */
|
|
|
|
|
return rb;
|
|
|
|
|
}
|
|
|
|
|
|
2014-06-15 18:47:07 +00:00
|
|
|
static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
|
|
|
|
|
bool is_base_size)
|
KVM: PPC: Only get pages when actually needed, not in prepare_memory_region()
This removes the code from kvmppc_core_prepare_memory_region() that
looked up the VMA for the region being added and called hva_to_page
to get the pfns for the memory. We have no guarantee that there will
be anything mapped there at the time of the KVM_SET_USER_MEMORY_REGION
ioctl call; userspace can do that ioctl and then map memory into the
region later.
Instead we defer looking up the pfn for each memory page until it is
needed, which generally means when the guest does an H_ENTER hcall on
the page. Since we can't call get_user_pages in real mode, if we don't
already have the pfn for the page, kvmppc_h_enter() will return
H_TOO_HARD and we then call kvmppc_virtmode_h_enter() once we get back
to kernel context. That calls kvmppc_get_guest_page() to get the pfn
for the page, and then calls back to kvmppc_h_enter() to redo the HPTE
insertion.
When the first vcpu starts executing, we need to have the RMO or VRMA
region mapped so that the guest's real mode accesses will work. Thus
we now have a check in kvmppc_vcpu_run() to see if the RMO/VRMA is set
up and if not, call kvmppc_hv_setup_rma(). It checks if the memslot
starting at guest physical 0 now has RMO memory mapped there; if so it
sets it up for the guest, otherwise on POWER7 it sets up the VRMA.
The function that does that, kvmppc_map_vrma, is now a bit simpler,
as it calls kvmppc_virtmode_h_enter instead of creating the HPTE itself.
Since we are now potentially updating entries in the slot_phys[]
arrays from multiple vcpu threads, we now have a spinlock protecting
those updates to ensure that we don't lose track of any references
to pages.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:31:00 +00:00
|
|
|
{
|
2014-06-15 18:47:07 +00:00
|
|
|
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
int size, a_psize;
|
|
|
|
|
/* Look at the 8 bit LP value */
|
|
|
|
|
unsigned int lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
|
|
|
|
|
|
KVM: PPC: Only get pages when actually needed, not in prepare_memory_region()
This removes the code from kvmppc_core_prepare_memory_region() that
looked up the VMA for the region being added and called hva_to_page
to get the pfns for the memory. We have no guarantee that there will
be anything mapped there at the time of the KVM_SET_USER_MEMORY_REGION
ioctl call; userspace can do that ioctl and then map memory into the
region later.
Instead we defer looking up the pfn for each memory page until it is
needed, which generally means when the guest does an H_ENTER hcall on
the page. Since we can't call get_user_pages in real mode, if we don't
already have the pfn for the page, kvmppc_h_enter() will return
H_TOO_HARD and we then call kvmppc_virtmode_h_enter() once we get back
to kernel context. That calls kvmppc_get_guest_page() to get the pfn
for the page, and then calls back to kvmppc_h_enter() to redo the HPTE
insertion.
When the first vcpu starts executing, we need to have the RMO or VRMA
region mapped so that the guest's real mode accesses will work. Thus
we now have a check in kvmppc_vcpu_run() to see if the RMO/VRMA is set
up and if not, call kvmppc_hv_setup_rma(). It checks if the memslot
starting at guest physical 0 now has RMO memory mapped there; if so it
sets it up for the guest, otherwise on POWER7 it sets up the VRMA.
The function that does that, kvmppc_map_vrma, is now a bit simpler,
as it calls kvmppc_virtmode_h_enter instead of creating the HPTE itself.
Since we are now potentially updating entries in the slot_phys[]
arrays from multiple vcpu threads, we now have a spinlock protecting
those updates to ensure that we don't lose track of any references
to pages.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:31:00 +00:00
|
|
|
/* only handle 4k, 64k and 16M pages for now */
|
|
|
|
|
if (!(h & HPTE_V_LARGE))
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
return 1ul << 12;
|
|
|
|
|
else {
|
|
|
|
|
for (size = 0; size < MMU_PAGE_COUNT; size++) {
|
|
|
|
|
/* valid entries have a shift value */
|
|
|
|
|
if (!mmu_psize_defs[size].shift)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
a_psize = __hpte_actual_psize(lp, size);
|
2014-06-15 18:47:07 +00:00
|
|
|
if (a_psize != -1) {
|
|
|
|
|
if (is_base_size)
|
|
|
|
|
return 1ul << mmu_psize_defs[size].shift;
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
return 1ul << mmu_psize_defs[a_psize].shift;
|
2014-06-15 18:47:07 +00:00
|
|
|
}
|
KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup is done using a 64kB page size, it may be necessary to
put multiple entries in the HPT for a single 16MB page. This
capability is called mixed page-size segment (MPSS). With MPSS,
there are two relevant page sizes: the base page size, which is the
size used in searching the HPT, and the actual page size, which is the
size indicated in the HPT entry. [ Note that the actual page size is
always >= base page size ].
We use "ibm,segment-page-sizes" device tree node to advertise
the MPSS support to PAPR guest. The penc encoding indicates whether
we support a specific combination of base page size and actual
page size in the same segment. We also use the penc value in the
LP encoding of HPTE entry.
This patch exposes MPSS support to KVM guest by advertising the
feature via "ibm,segment-page-sizes". It also adds the necessary changes
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-06 18:01:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
KVM: PPC: Only get pages when actually needed, not in prepare_memory_region()
This removes the code from kvmppc_core_prepare_memory_region() that
looked up the VMA for the region being added and called hva_to_page
to get the pfns for the memory. We have no guarantee that there will
be anything mapped there at the time of the KVM_SET_USER_MEMORY_REGION
ioctl call; userspace can do that ioctl and then map memory into the
region later.
Instead we defer looking up the pfn for each memory page until it is
needed, which generally means when the guest does an H_ENTER hcall on
the page. Since we can't call get_user_pages in real mode, if we don't
already have the pfn for the page, kvmppc_h_enter() will return
H_TOO_HARD and we then call kvmppc_virtmode_h_enter() once we get back
to kernel context. That calls kvmppc_get_guest_page() to get the pfn
for the page, and then calls back to kvmppc_h_enter() to redo the HPTE
insertion.
When the first vcpu starts executing, we need to have the RMO or VRMA
region mapped so that the guest's real mode accesses will work. Thus
we now have a check in kvmppc_vcpu_run() to see if the RMO/VRMA is set
up and if not, call kvmppc_hv_setup_rma(). It checks if the memslot
starting at guest physical 0 now has RMO memory mapped there; if so it
sets it up for the guest, otherwise on POWER7 it sets up the VRMA.
The function that does that, kvmppc_map_vrma, is now a bit simpler,
as it calls kvmppc_virtmode_h_enter instead of creating the HPTE itself.
Since we are now potentially updating entries in the slot_phys[]
arrays from multiple vcpu threads, we now have a spinlock protecting
those updates to ensure that we don't lose track of any references
to pages.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:31:00 +00:00
|
|
|
}
|
|
|
|
|
|
2014-06-15 18:47:07 +00:00
|
|
|
static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
|
|
|
|
|
{
|
|
|
|
|
return __hpte_page_size(h, l, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
|
|
|
|
|
{
|
|
|
|
|
return __hpte_page_size(h, l, 1);
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-12 12:33:07 +00:00
|
|
|
static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
|
|
|
|
|
{
|
|
|
|
|
return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-12 12:38:51 +00:00
|
|
|
static inline int hpte_is_writable(unsigned long ptel)
|
|
|
|
|
{
|
|
|
|
|
unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
|
|
|
|
|
|
|
|
|
|
return pp != PP_RXRX && pp != PP_RXXX;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned long hpte_make_readonly(unsigned long ptel)
|
|
|
|
|
{
|
|
|
|
|
if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
|
|
|
|
|
ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
|
|
|
|
|
else
|
|
|
|
|
ptel |= PP_RXRX;
|
|
|
|
|
return ptel;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-12 12:32:27 +00:00
|
|
|
static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
|
|
|
|
|
{
|
|
|
|
|
unsigned int wimg = ptel & HPTE_R_WIMG;
|
|
|
|
|
|
|
|
|
|
/* Handle SAO */
|
|
|
|
|
if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
|
|
|
|
|
cpu_has_feature(CPU_FTR_ARCH_206))
|
|
|
|
|
wimg = HPTE_R_M;
|
|
|
|
|
|
|
|
|
|
if (!io_type)
|
|
|
|
|
return wimg == HPTE_R_M;
|
|
|
|
|
|
|
|
|
|
return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
|
|
|
|
|
}
|
|
|
|
|
|
KVM: PPC: Implement MMU notifiers for Book3S HV guests
This adds the infrastructure to enable us to page out pages underneath
a Book3S HV guest, on processors that support virtualized partition
memory, that is, POWER7. Instead of pinning all the guest's pages,
we now look in the host userspace Linux page tables to find the
mapping for a given guest page. Then, if the userspace Linux PTE
gets invalidated, kvm_unmap_hva() gets called for that address, and
we replace all the guest HPTEs that refer to that page with absent
HPTEs, i.e. ones with the valid bit clear and the HPTE_V_ABSENT bit
set, which will cause an HDSI when the guest tries to access them.
Finally, the page fault handler is extended to reinstantiate the
guest HPTE when the guest tries to access a page which has been paged
out.
Since we can't intercept the guest DSI and ISI interrupts on PPC970,
we still have to pin all the guest pages on PPC970. We have a new flag,
kvm->arch.using_mmu_notifiers, that indicates whether we can page
guest pages out. If it is not set, the MMU notifier callbacks do
nothing and everything operates as before.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:38:05 +00:00
|
|
|
/*
|
2013-06-20 09:00:19 +00:00
|
|
|
* If it's present and writable, atomically set dirty and referenced bits and
|
|
|
|
|
* return the PTE, otherwise return 0. If we find a transparent hugepage
|
|
|
|
|
* and if it is marked splitting we return 0;
|
KVM: PPC: Implement MMU notifiers for Book3S HV guests
This adds the infrastructure to enable us to page out pages underneath
a Book3S HV guest, on processors that support virtualized partition
memory, that is, POWER7. Instead of pinning all the guest's pages,
we now look in the host userspace Linux page tables to find the
mapping for a given guest page. Then, if the userspace Linux PTE
gets invalidated, kvm_unmap_hva() gets called for that address, and
we replace all the guest HPTEs that refer to that page with absent
HPTEs, i.e. ones with the valid bit clear and the HPTE_V_ABSENT bit
set, which will cause an HDSI when the guest tries to access them.
Finally, the page fault handler is extended to reinstantiate the
guest HPTE when the guest tries to access a page which has been paged
out.
Since we can't intercept the guest DSI and ISI interrupts on PPC970,
we still have to pin all the guest pages on PPC970. We have a new flag,
kvm->arch.using_mmu_notifiers, that indicates whether we can page
guest pages out. If it is not set, the MMU notifier callbacks do
nothing and everything operates as before.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:38:05 +00:00
|
|
|
*/
|
2013-06-20 09:00:19 +00:00
|
|
|
static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
|
|
|
|
|
unsigned int hugepage)
|
KVM: PPC: Implement MMU notifiers for Book3S HV guests
This adds the infrastructure to enable us to page out pages underneath
a Book3S HV guest, on processors that support virtualized partition
memory, that is, POWER7. Instead of pinning all the guest's pages,
we now look in the host userspace Linux page tables to find the
mapping for a given guest page. Then, if the userspace Linux PTE
gets invalidated, kvm_unmap_hva() gets called for that address, and
we replace all the guest HPTEs that refer to that page with absent
HPTEs, i.e. ones with the valid bit clear and the HPTE_V_ABSENT bit
set, which will cause an HDSI when the guest tries to access them.
Finally, the page fault handler is extended to reinstantiate the
guest HPTE when the guest tries to access a page which has been paged
out.
Since we can't intercept the guest DSI and ISI interrupts on PPC970,
we still have to pin all the guest pages on PPC970. We have a new flag,
kvm->arch.using_mmu_notifiers, that indicates whether we can page
guest pages out. If it is not set, the MMU notifier callbacks do
nothing and everything operates as before.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:38:05 +00:00
|
|
|
{
|
2013-06-20 09:00:19 +00:00
|
|
|
pte_t old_pte, new_pte = __pte(0);
|
|
|
|
|
|
|
|
|
|
while (1) {
|
2015-03-25 09:11:57 +00:00
|
|
|
old_pte = *ptep;
|
2013-06-20 09:00:19 +00:00
|
|
|
/*
|
|
|
|
|
* wait until _PAGE_BUSY is clear then set it atomically
|
|
|
|
|
*/
|
2015-03-25 09:11:57 +00:00
|
|
|
if (unlikely(pte_val(old_pte) & _PAGE_BUSY)) {
|
2013-06-20 09:00:19 +00:00
|
|
|
cpu_relax();
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
|
|
|
|
/* If hugepage and is trans splitting return None */
|
|
|
|
|
if (unlikely(hugepage &&
|
|
|
|
|
pmd_trans_splitting(pte_pmd(old_pte))))
|
|
|
|
|
return __pte(0);
|
|
|
|
|
#endif
|
|
|
|
|
/* If pte is not present return None */
|
2015-03-25 09:11:57 +00:00
|
|
|
if (unlikely(!(pte_val(old_pte) & _PAGE_PRESENT)))
|
2013-06-20 09:00:19 +00:00
|
|
|
return __pte(0);
|
KVM: PPC: Implement MMU notifiers for Book3S HV guests
This adds the infrastructure to enable us to page out pages underneath
a Book3S HV guest, on processors that support virtualized partition
memory, that is, POWER7. Instead of pinning all the guest's pages,
we now look in the host userspace Linux page tables to find the
mapping for a given guest page. Then, if the userspace Linux PTE
gets invalidated, kvm_unmap_hva() gets called for that address, and
we replace all the guest HPTEs that refer to that page with absent
HPTEs, i.e. ones with the valid bit clear and the HPTE_V_ABSENT bit
set, which will cause an HDSI when the guest tries to access them.
Finally, the page fault handler is extended to reinstantiate the
guest HPTE when the guest tries to access a page which has been paged
out.
Since we can't intercept the guest DSI and ISI interrupts on PPC970,
we still have to pin all the guest pages on PPC970. We have a new flag,
kvm->arch.using_mmu_notifiers, that indicates whether we can page
guest pages out. If it is not set, the MMU notifier callbacks do
nothing and everything operates as before.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:38:05 +00:00
|
|
|
|
2013-06-20 09:00:19 +00:00
|
|
|
new_pte = pte_mkyoung(old_pte);
|
|
|
|
|
if (writing && pte_write(old_pte))
|
|
|
|
|
new_pte = pte_mkdirty(new_pte);
|
KVM: PPC: Implement MMU notifiers for Book3S HV guests
This adds the infrastructure to enable us to page out pages underneath
a Book3S HV guest, on processors that support virtualized partition
memory, that is, POWER7. Instead of pinning all the guest's pages,
we now look in the host userspace Linux page tables to find the
mapping for a given guest page. Then, if the userspace Linux PTE
gets invalidated, kvm_unmap_hva() gets called for that address, and
we replace all the guest HPTEs that refer to that page with absent
HPTEs, i.e. ones with the valid bit clear and the HPTE_V_ABSENT bit
set, which will cause an HDSI when the guest tries to access them.
Finally, the page fault handler is extended to reinstantiate the
guest HPTE when the guest tries to access a page which has been paged
out.
Since we can't intercept the guest DSI and ISI interrupts on PPC970,
we still have to pin all the guest pages on PPC970. We have a new flag,
kvm->arch.using_mmu_notifiers, that indicates whether we can page
guest pages out. If it is not set, the MMU notifier callbacks do
nothing and everything operates as before.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:38:05 +00:00
|
|
|
|
2015-03-25 09:11:57 +00:00
|
|
|
if (pte_val(old_pte) == __cmpxchg_u64((unsigned long *)ptep,
|
|
|
|
|
pte_val(old_pte),
|
|
|
|
|
pte_val(new_pte))) {
|
2013-06-20 09:00:19 +00:00
|
|
|
break;
|
2015-03-25 09:11:57 +00:00
|
|
|
}
|
2013-06-20 09:00:19 +00:00
|
|
|
}
|
|
|
|
|
return new_pte;
|
KVM: PPC: Implement MMU notifiers for Book3S HV guests
This adds the infrastructure to enable us to page out pages underneath
a Book3S HV guest, on processors that support virtualized partition
memory, that is, POWER7. Instead of pinning all the guest's pages,
we now look in the host userspace Linux page tables to find the
mapping for a given guest page. Then, if the userspace Linux PTE
gets invalidated, kvm_unmap_hva() gets called for that address, and
we replace all the guest HPTEs that refer to that page with absent
HPTEs, i.e. ones with the valid bit clear and the HPTE_V_ABSENT bit
set, which will cause an HDSI when the guest tries to access them.
Finally, the page fault handler is extended to reinstantiate the
guest HPTE when the guest tries to access a page which has been paged
out.
Since we can't intercept the guest DSI and ISI interrupts on PPC970,
we still have to pin all the guest pages on PPC970. We have a new flag,
kvm->arch.using_mmu_notifiers, that indicates whether we can page
guest pages out. If it is not set, the MMU notifier callbacks do
nothing and everything operates as before.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:38:05 +00:00
|
|
|
}
|
|
|
|
|
|
2013-06-20 09:00:19 +00:00
|
|
|
|
2011-12-12 12:32:27 +00:00
|
|
|
/* Return HPTE cache control bits corresponding to Linux pte bits */
|
|
|
|
|
static inline unsigned long hpte_cache_bits(unsigned long pte_val)
|
|
|
|
|
{
|
|
|
|
|
#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
|
|
|
|
|
return pte_val & (HPTE_R_W | HPTE_R_I);
|
|
|
|
|
#else
|
|
|
|
|
return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
|
|
|
|
|
((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
KVM: PPC: Implement MMIO emulation support for Book3S HV guests
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page. An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.
When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.
This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:36:37 +00:00
|
|
|
static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
|
|
|
|
|
{
|
|
|
|
|
if (key)
|
|
|
|
|
return PP_RWRX <= pp && pp <= PP_RXRX;
|
2015-03-30 23:46:04 +00:00
|
|
|
return true;
|
KVM: PPC: Implement MMIO emulation support for Book3S HV guests
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page. An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.
When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.
This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:36:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
|
|
|
|
|
{
|
|
|
|
|
if (key)
|
|
|
|
|
return pp == PP_RWRW;
|
|
|
|
|
return pp <= PP_RWRW;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
|
|
|
|
|
{
|
|
|
|
|
unsigned long skey;
|
|
|
|
|
|
|
|
|
|
skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
|
|
|
|
|
((hpte_r & HPTE_R_KEY_LO) >> 9);
|
|
|
|
|
return (amr >> (62 - 2 * skey)) & 3;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-12 12:33:07 +00:00
|
|
|
static inline void lock_rmap(unsigned long *rmap)
|
|
|
|
|
{
|
|
|
|
|
do {
|
|
|
|
|
while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
|
|
|
|
|
cpu_relax();
|
|
|
|
|
} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void unlock_rmap(unsigned long *rmap)
|
|
|
|
|
{
|
|
|
|
|
__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-12 12:31:41 +00:00
|
|
|
static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
|
|
|
|
|
unsigned long pagesize)
|
|
|
|
|
{
|
|
|
|
|
unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
|
|
|
|
|
|
|
|
|
|
if (pagesize <= PAGE_SIZE)
|
2015-03-30 23:46:04 +00:00
|
|
|
return true;
|
2011-12-12 12:31:41 +00:00
|
|
|
return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
|
|
|
|
|
}
|
|
|
|
|
|
KVM: PPC: Book3S HV: Provide a method for userspace to read and write the HPT
A new ioctl, KVM_PPC_GET_HTAB_FD, returns a file descriptor. Reads on
this fd return the contents of the HPT (hashed page table), writes
create and/or remove entries in the HPT. There is a new capability,
KVM_CAP_PPC_HTAB_FD, to indicate the presence of the ioctl. The ioctl
takes an argument structure with the index of the first HPT entry to
read out and a set of flags. The flags indicate whether the user is
intending to read or write the HPT, and whether to return all entries
or only the "bolted" entries (those with the bolted bit, 0x10, set in
the first doubleword).
This is intended for use in implementing qemu's savevm/loadvm and for
live migration. Therefore, on reads, the first pass returns information
about all HPTEs (or all bolted HPTEs). When the first pass reaches the
end of the HPT, it returns from the read. Subsequent reads only return
information about HPTEs that have changed since they were last read.
A read that finds no changed HPTEs in the HPT following where the last
read finished will return 0 bytes.
The format of the data provides a simple run-length compression of the
invalid entries. Each block of data starts with a header that indicates
the index (position in the HPT, which is just an array), the number of
valid entries starting at that index (may be zero), and the number of
invalid entries following those valid entries. The valid entries, 16
bytes each, follow the header. The invalid entries are not explicitly
represented.
Signed-off-by: Paul Mackerras <paulus@samba.org>
[agraf: fix documentation]
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-19 22:57:20 +00:00
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/*
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* This works for 4k, 64k and 16M pages on POWER7,
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* and 4k and 16M pages on PPC970.
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*/
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static inline unsigned long slb_pgsize_encoding(unsigned long psize)
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{
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unsigned long senc = 0;
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if (psize > 0x1000) {
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senc = SLB_VSID_L;
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if (psize == 0x10000)
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senc |= SLB_VSID_LP_01;
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}
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return senc;
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}
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static inline int is_vrma_hpte(unsigned long hpte_v)
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{
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return (hpte_v & ~0xffffffUL) ==
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(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
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}
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2013-10-07 16:47:52 +00:00
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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2013-04-18 19:50:24 +00:00
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/*
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* Note modification of an HPTE; set the HPTE modified bit
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* if anyone is interested.
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*/
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static inline void note_hpte_modification(struct kvm *kvm,
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struct revmap_entry *rev)
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{
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if (atomic_read(&kvm->arch.hpte_mod_interest))
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rev->guest_rpte |= HPTE_GR_MODIFIED;
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}
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KVM: PPC: Book3S HV: Don't use kvm_memslots() in real mode
With HV KVM, some high-frequency hypercalls such as H_ENTER are handled
in real mode, and need to access the memslots array for the guest.
Accessing the memslots array is safe, because we hold the SRCU read
lock for the whole time that a guest vcpu is running. However, the
checks that kvm_memslots() does when lockdep is enabled are potentially
unsafe in real mode, when only the linear mapping is available.
Furthermore, kvm_memslots() can be called from a secondary CPU thread,
which is an offline CPU from the point of view of the host kernel,
and is not running the task which holds the SRCU read lock.
To avoid false positives in the checks in kvm_memslots(), and to avoid
possible side effects from doing the checks in real mode, this replaces
kvm_memslots() with kvm_memslots_raw() in all the places that execute
in real mode. kvm_memslots_raw() is a new function that is like
kvm_memslots() but uses rcu_dereference_raw_notrace() instead of
kvm_dereference_check().
Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-24 23:47:06 +00:00
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/*
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* Like kvm_memslots(), but for use in real mode when we can't do
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* any RCU stuff (since the secondary threads are offline from the
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* kernel's point of view), and we can't print anything.
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* Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
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*/
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static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
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{
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return rcu_dereference_raw_notrace(kvm->memslots);
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}
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2013-10-07 16:47:52 +00:00
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#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
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2013-04-18 19:50:24 +00:00
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2010-04-15 22:11:37 +00:00
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#endif /* __ASM_KVM_BOOK3S_64_H__ */
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