2018-08-22 20:41:03 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0
|
2008-04-16 01:56:35 +00:00
|
|
|
/*
|
|
|
|
* Generic EP93xx GPIO handling
|
|
|
|
*
|
2011-06-15 04:45:36 +00:00
|
|
|
* Copyright (c) 2008 Ryan Mallon
|
2011-06-08 21:35:33 +00:00
|
|
|
* Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
|
2008-04-16 01:56:35 +00:00
|
|
|
*
|
|
|
|
* Based on code originally from:
|
|
|
|
* linux/arch/arm/mach-ep93xx/core.c
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/init.h>
|
2011-07-03 17:38:09 +00:00
|
|
|
#include <linux/module.h>
|
2011-06-08 21:35:33 +00:00
|
|
|
#include <linux/platform_device.h>
|
2008-09-06 11:10:45 +00:00
|
|
|
#include <linux/io.h>
|
2009-07-15 20:31:46 +00:00
|
|
|
#include <linux/irq.h>
|
2011-06-08 21:35:33 +00:00
|
|
|
#include <linux/slab.h>
|
2015-12-04 13:02:58 +00:00
|
|
|
#include <linux/gpio/driver.h>
|
2018-08-22 20:41:08 +00:00
|
|
|
#include <linux/bitops.h>
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
#define EP93XX_GPIO_F_INT_STATUS 0x5c
|
|
|
|
#define EP93XX_GPIO_A_INT_STATUS 0xa0
|
|
|
|
#define EP93XX_GPIO_B_INT_STATUS 0xbc
|
2018-08-22 20:41:01 +00:00
|
|
|
|
|
|
|
/* Maximum value for gpio line identifiers */
|
|
|
|
#define EP93XX_GPIO_LINE_MAX 63
|
|
|
|
|
|
|
|
/* Maximum value for irq capable line identifiers */
|
|
|
|
#define EP93XX_GPIO_LINE_MAX_IRQ 23
|
|
|
|
|
2018-08-22 20:41:10 +00:00
|
|
|
/*
|
2018-08-22 20:41:11 +00:00
|
|
|
* Static mapping of GPIO bank F IRQS:
|
|
|
|
* F0..F7 (16..24) to irq 80..87.
|
2018-08-22 20:41:10 +00:00
|
|
|
*/
|
2018-08-22 20:41:11 +00:00
|
|
|
#define EP93XX_GPIO_F_IRQ_BASE 80
|
2018-08-22 20:41:10 +00:00
|
|
|
|
2011-06-08 21:35:33 +00:00
|
|
|
struct ep93xx_gpio {
|
2018-08-22 20:41:02 +00:00
|
|
|
void __iomem *base;
|
2015-12-04 13:02:58 +00:00
|
|
|
struct gpio_chip gc[8];
|
2011-06-08 21:35:33 +00:00
|
|
|
};
|
|
|
|
|
2010-02-23 20:41:17 +00:00
|
|
|
/*************************************************************************
|
2010-04-06 21:46:16 +00:00
|
|
|
* Interrupt handling for EP93xx on-chip GPIOs
|
2010-02-23 20:41:17 +00:00
|
|
|
*************************************************************************/
|
|
|
|
static unsigned char gpio_int_unmasked[3];
|
|
|
|
static unsigned char gpio_int_enabled[3];
|
|
|
|
static unsigned char gpio_int_type1[3];
|
|
|
|
static unsigned char gpio_int_type2[3];
|
|
|
|
static unsigned char gpio_int_debounce[3];
|
|
|
|
|
|
|
|
/* Port ordering is: A B F */
|
|
|
|
static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
|
|
|
|
static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
|
|
|
|
static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
|
|
|
|
static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
|
|
|
|
static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
|
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
|
|
|
BUG_ON(port > 2);
|
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
writeb_relaxed(0, epg->base + int_en_register_offset[port]);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2013-10-14 08:07:08 +00:00
|
|
|
writeb_relaxed(gpio_int_type2[port],
|
2018-08-22 20:41:04 +00:00
|
|
|
epg->base + int_type2_register_offset[port]);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2013-10-14 08:07:08 +00:00
|
|
|
writeb_relaxed(gpio_int_type1[port],
|
2018-08-22 20:41:04 +00:00
|
|
|
epg->base + int_type1_register_offset[port]);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2013-10-14 08:07:08 +00:00
|
|
|
writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
|
2018-08-22 20:41:04 +00:00
|
|
|
epg->base + int_en_register_offset[port]);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2018-08-22 20:41:07 +00:00
|
|
|
static int ep93xx_gpio_port(struct gpio_chip *gc)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
2018-08-22 20:41:07 +00:00
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
|
|
|
int port = 0;
|
|
|
|
|
2018-09-06 11:58:30 +00:00
|
|
|
while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port])
|
2018-08-22 20:41:07 +00:00
|
|
|
port++;
|
|
|
|
|
|
|
|
/* This should not happen but is there as a last safeguard */
|
2018-09-06 13:33:48 +00:00
|
|
|
if (port == ARRAY_SIZE(epg->gc)) {
|
2018-08-22 20:41:07 +00:00
|
|
|
pr_crit("can't find the GPIO port\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return port;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
|
|
|
|
unsigned int offset, bool enable)
|
|
|
|
{
|
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
|
|
|
int port = ep93xx_gpio_port(gc);
|
|
|
|
int port_mask = BIT(offset);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
|
|
|
if (enable)
|
|
|
|
gpio_int_debounce[port] |= port_mask;
|
|
|
|
else
|
|
|
|
gpio_int_debounce[port] &= ~port_mask;
|
|
|
|
|
2013-10-14 08:07:08 +00:00
|
|
|
writeb(gpio_int_debounce[port],
|
2018-08-22 20:41:04 +00:00
|
|
|
epg->base + int_debounce_register_offset[port]);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2015-09-14 08:42:37 +00:00
|
|
|
static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
2018-08-22 20:41:04 +00:00
|
|
|
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
2018-08-22 20:41:06 +00:00
|
|
|
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
2018-08-22 20:41:09 +00:00
|
|
|
unsigned long stat;
|
|
|
|
int offset;
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:06 +00:00
|
|
|
chained_irq_enter(irqchip, desc);
|
|
|
|
|
2018-08-22 20:41:11 +00:00
|
|
|
/*
|
|
|
|
* Dispatch the IRQs to the irqdomain of each A and B
|
|
|
|
* gpiochip irqdomains depending on what has fired.
|
|
|
|
* The tricky part is that the IRQ line is shared
|
|
|
|
* between bank A and B and each has their own gpiochip.
|
|
|
|
*/
|
2018-08-22 20:41:09 +00:00
|
|
|
stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
|
2018-08-22 20:41:11 +00:00
|
|
|
for_each_set_bit(offset, &stat, 8)
|
|
|
|
generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain,
|
|
|
|
offset));
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:09 +00:00
|
|
|
stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
|
2018-08-22 20:41:11 +00:00
|
|
|
for_each_set_bit(offset, &stat, 8)
|
|
|
|
generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain,
|
|
|
|
offset));
|
2018-08-22 20:41:06 +00:00
|
|
|
|
|
|
|
chained_irq_exit(irqchip, desc);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2015-09-14 08:42:37 +00:00
|
|
|
static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
|
|
|
/*
|
2011-03-31 01:57:33 +00:00
|
|
|
* map discontiguous hw irq range to continuous sw irq range:
|
2010-02-23 20:41:17 +00:00
|
|
|
*
|
2018-08-22 20:41:10 +00:00
|
|
|
* IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
|
2010-02-23 20:41:17 +00:00
|
|
|
*/
|
2018-08-22 20:41:06 +00:00
|
|
|
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
2015-07-12 22:06:41 +00:00
|
|
|
unsigned int irq = irq_desc_get_irq(desc);
|
2010-02-23 20:41:17 +00:00
|
|
|
int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
|
2018-08-22 20:41:11 +00:00
|
|
|
int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:06 +00:00
|
|
|
chained_irq_enter(irqchip, desc);
|
2010-02-23 20:41:17 +00:00
|
|
|
generic_handle_irq(gpio_irq);
|
2018-08-22 20:41:06 +00:00
|
|
|
chained_irq_exit(irqchip, desc);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2010-11-29 09:29:50 +00:00
|
|
|
static void ep93xx_gpio_irq_ack(struct irq_data *d)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
2018-08-22 20:41:04 +00:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
2018-08-22 20:41:08 +00:00
|
|
|
int port = ep93xx_gpio_port(gc);
|
|
|
|
int port_mask = BIT(d->irq & 7);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2011-03-24 11:45:56 +00:00
|
|
|
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
|
2010-02-23 20:41:17 +00:00
|
|
|
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
|
2018-08-22 20:41:04 +00:00
|
|
|
ep93xx_gpio_update_int_params(epg, port);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
writeb(port_mask, epg->base + eoi_register_offset[port]);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2010-11-29 09:29:50 +00:00
|
|
|
static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
2018-08-22 20:41:04 +00:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
2018-08-22 20:41:08 +00:00
|
|
|
int port = ep93xx_gpio_port(gc);
|
|
|
|
int port_mask = BIT(d->irq & 7);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2011-03-24 11:45:56 +00:00
|
|
|
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
|
2010-02-23 20:41:17 +00:00
|
|
|
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
|
|
|
|
|
|
|
|
gpio_int_unmasked[port] &= ~port_mask;
|
2018-08-22 20:41:04 +00:00
|
|
|
ep93xx_gpio_update_int_params(epg, port);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
writeb(port_mask, epg->base + eoi_register_offset[port]);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2010-11-29 09:29:50 +00:00
|
|
|
static void ep93xx_gpio_irq_mask(struct irq_data *d)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
2018-08-22 20:41:04 +00:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
2018-08-22 20:41:08 +00:00
|
|
|
int port = ep93xx_gpio_port(gc);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:08 +00:00
|
|
|
gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
|
2018-08-22 20:41:04 +00:00
|
|
|
ep93xx_gpio_update_int_params(epg, port);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
2010-11-29 09:29:50 +00:00
|
|
|
static void ep93xx_gpio_irq_unmask(struct irq_data *d)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
2018-08-22 20:41:04 +00:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
2018-08-22 20:41:08 +00:00
|
|
|
int port = ep93xx_gpio_port(gc);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:08 +00:00
|
|
|
gpio_int_unmasked[port] |= BIT(d->irq & 7);
|
2018-08-22 20:41:04 +00:00
|
|
|
ep93xx_gpio_update_int_params(epg, port);
|
2010-02-23 20:41:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* gpio_int_type1 controls whether the interrupt is level (0) or
|
|
|
|
* edge (1) triggered, while gpio_int_type2 controls whether it
|
|
|
|
* triggers on low/falling (0) or high/rising (1).
|
|
|
|
*/
|
2010-11-29 09:29:50 +00:00
|
|
|
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
|
2010-02-23 20:41:17 +00:00
|
|
|
{
|
2018-08-22 20:41:04 +00:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
2018-08-22 20:41:08 +00:00
|
|
|
int port = ep93xx_gpio_port(gc);
|
|
|
|
int offset = d->irq & 7;
|
|
|
|
int port_mask = BIT(offset);
|
2011-03-24 11:45:56 +00:00
|
|
|
irq_flow_handler_t handler;
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:08 +00:00
|
|
|
gc->direction_input(gc, offset);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
|
|
gpio_int_type1[port] |= port_mask;
|
|
|
|
gpio_int_type2[port] |= port_mask;
|
2011-03-24 11:45:56 +00:00
|
|
|
handler = handle_edge_irq;
|
2010-02-23 20:41:17 +00:00
|
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
|
|
gpio_int_type1[port] |= port_mask;
|
|
|
|
gpio_int_type2[port] &= ~port_mask;
|
2011-03-24 11:45:56 +00:00
|
|
|
handler = handle_edge_irq;
|
2010-02-23 20:41:17 +00:00
|
|
|
break;
|
|
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
|
|
gpio_int_type1[port] &= ~port_mask;
|
|
|
|
gpio_int_type2[port] |= port_mask;
|
2011-03-24 11:45:56 +00:00
|
|
|
handler = handle_level_irq;
|
2010-02-23 20:41:17 +00:00
|
|
|
break;
|
|
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
|
|
gpio_int_type1[port] &= ~port_mask;
|
|
|
|
gpio_int_type2[port] &= ~port_mask;
|
2011-03-24 11:45:56 +00:00
|
|
|
handler = handle_level_irq;
|
2010-02-23 20:41:17 +00:00
|
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
|
|
gpio_int_type1[port] |= port_mask;
|
|
|
|
/* set initial polarity based on current input level */
|
2018-08-22 20:41:08 +00:00
|
|
|
if (gc->get(gc, offset))
|
2010-02-23 20:41:17 +00:00
|
|
|
gpio_int_type2[port] &= ~port_mask; /* falling */
|
|
|
|
else
|
|
|
|
gpio_int_type2[port] |= port_mask; /* rising */
|
2011-03-24 11:45:56 +00:00
|
|
|
handler = handle_edge_irq;
|
2010-02-23 20:41:17 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2015-06-23 13:52:38 +00:00
|
|
|
irq_set_handler_locked(d, handler);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2011-03-24 11:45:56 +00:00
|
|
|
gpio_int_enabled[port] |= port_mask;
|
2010-02-23 20:41:17 +00:00
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
ep93xx_gpio_update_int_params(epg, port);
|
2010-02-23 20:41:17 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct irq_chip ep93xx_gpio_irq_chip = {
|
|
|
|
.name = "GPIO",
|
2010-11-29 09:29:50 +00:00
|
|
|
.irq_ack = ep93xx_gpio_irq_ack,
|
|
|
|
.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
|
|
|
|
.irq_mask = ep93xx_gpio_irq_mask,
|
|
|
|
.irq_unmask = ep93xx_gpio_irq_unmask,
|
|
|
|
.irq_set_type = ep93xx_gpio_irq_type,
|
2010-02-23 20:41:17 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*************************************************************************
|
|
|
|
* gpiolib interface for EP93xx on-chip GPIOs
|
|
|
|
*************************************************************************/
|
2011-06-08 21:35:33 +00:00
|
|
|
struct ep93xx_gpio_bank {
|
|
|
|
const char *label;
|
|
|
|
int data;
|
|
|
|
int dir;
|
|
|
|
int base;
|
2018-08-22 20:41:05 +00:00
|
|
|
bool has_irq;
|
2019-08-12 13:00:00 +00:00
|
|
|
bool has_hierarchical_irq;
|
|
|
|
unsigned int irq_base;
|
2008-04-16 01:56:35 +00:00
|
|
|
};
|
|
|
|
|
2019-08-12 13:00:00 +00:00
|
|
|
#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, _irq_base) \
|
2011-06-08 21:35:33 +00:00
|
|
|
{ \
|
|
|
|
.label = _label, \
|
|
|
|
.data = _data, \
|
|
|
|
.dir = _dir, \
|
|
|
|
.base = _base, \
|
2018-08-22 20:41:05 +00:00
|
|
|
.has_irq = _has_irq, \
|
2019-08-12 13:00:00 +00:00
|
|
|
.has_hierarchical_irq = _has_hier, \
|
|
|
|
.irq_base = _irq_base, \
|
2011-06-08 21:35:33 +00:00
|
|
|
}
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2011-06-08 21:35:33 +00:00
|
|
|
static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
|
2019-08-12 13:00:00 +00:00
|
|
|
/* Bank A has 8 IRQs */
|
|
|
|
EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64),
|
|
|
|
/* Bank B has 8 IRQs */
|
|
|
|
EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72),
|
|
|
|
EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0),
|
|
|
|
EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0),
|
|
|
|
EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0),
|
|
|
|
/* Bank F has 8 IRQs */
|
|
|
|
EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0),
|
|
|
|
EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0),
|
|
|
|
EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0),
|
2011-06-08 21:35:33 +00:00
|
|
|
};
|
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
|
2017-01-23 12:34:34 +00:00
|
|
|
unsigned long config)
|
2008-04-16 01:56:35 +00:00
|
|
|
{
|
2017-01-23 12:34:34 +00:00
|
|
|
u32 debounce;
|
|
|
|
|
|
|
|
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
|
|
|
|
return -ENOTSUPP;
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2017-01-23 12:34:34 +00:00
|
|
|
debounce = pinconf_to_config_argument(config);
|
2018-08-22 20:41:07 +00:00
|
|
|
ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
|
2008-04-16 01:56:35 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-08-22 20:41:11 +00:00
|
|
|
static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
|
2011-08-22 07:43:04 +00:00
|
|
|
{
|
2018-08-22 20:41:11 +00:00
|
|
|
return EP93XX_GPIO_F_IRQ_BASE + offset;
|
2011-08-22 07:43:04 +00:00
|
|
|
}
|
|
|
|
|
2019-08-12 13:00:00 +00:00
|
|
|
static int ep93xx_gpio_add_bank(struct gpio_chip *gc,
|
|
|
|
struct platform_device *pdev,
|
2018-08-22 20:41:04 +00:00
|
|
|
struct ep93xx_gpio *epg,
|
|
|
|
struct ep93xx_gpio_bank *bank)
|
2008-04-16 01:56:35 +00:00
|
|
|
{
|
2018-08-22 20:41:04 +00:00
|
|
|
void __iomem *data = epg->base + bank->data;
|
|
|
|
void __iomem *dir = epg->base + bank->dir;
|
2019-08-12 13:00:00 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct gpio_irq_chip *girq;
|
2011-06-08 21:35:33 +00:00
|
|
|
int err;
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2015-12-04 13:02:58 +00:00
|
|
|
err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
|
2011-06-08 21:35:33 +00:00
|
|
|
if (err)
|
|
|
|
return err;
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2015-12-04 13:02:58 +00:00
|
|
|
gc->label = bank->label;
|
|
|
|
gc->base = bank->base;
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2019-08-12 13:00:00 +00:00
|
|
|
girq = &gc->irq;
|
|
|
|
if (bank->has_irq || bank->has_hierarchical_irq) {
|
2017-01-23 12:34:34 +00:00
|
|
|
gc->set_config = ep93xx_gpio_set_config;
|
2019-08-12 13:00:00 +00:00
|
|
|
girq->chip = &ep93xx_gpio_irq_chip;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (bank->has_irq) {
|
|
|
|
int ab_parent_irq = platform_get_irq(pdev, 0);
|
|
|
|
|
|
|
|
girq->parent_handler = ep93xx_gpio_ab_irq_handler;
|
|
|
|
girq->num_parents = 1;
|
|
|
|
girq->parents = devm_kcalloc(dev, 1,
|
|
|
|
sizeof(*girq->parents),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!girq->parents)
|
|
|
|
return -ENOMEM;
|
|
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
|
|
girq->handler = handle_level_irq;
|
|
|
|
girq->parents[0] = ab_parent_irq;
|
|
|
|
girq->first = bank->irq_base;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Only bank F has especially funky IRQ handling */
|
|
|
|
if (bank->has_hierarchical_irq) {
|
|
|
|
int gpio_irq;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: convert this to use hierarchical IRQ support!
|
|
|
|
* this requires fixing the root irqchip to be hierarchial.
|
|
|
|
*/
|
|
|
|
girq->parent_handler = ep93xx_gpio_f_irq_handler;
|
|
|
|
girq->num_parents = 8;
|
|
|
|
girq->parents = devm_kcalloc(dev, 8,
|
|
|
|
sizeof(*girq->parents),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!girq->parents)
|
|
|
|
return -ENOMEM;
|
|
|
|
/* Pick resources 1..8 for these IRQs */
|
|
|
|
for (i = 1; i <= 8; i++)
|
|
|
|
girq->parents[i - 1] = platform_get_irq(pdev, i);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
|
|
|
|
irq_set_chip_data(gpio_irq, &epg->gc[5]);
|
|
|
|
irq_set_chip_and_handler(gpio_irq,
|
|
|
|
&ep93xx_gpio_irq_chip,
|
|
|
|
handle_level_irq);
|
|
|
|
irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
|
|
|
|
}
|
|
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
|
|
girq->handler = handle_level_irq;
|
|
|
|
gc->to_irq = ep93xx_gpio_f_to_irq;
|
|
|
|
}
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2018-08-22 20:41:04 +00:00
|
|
|
return devm_gpiochip_add_data(dev, gc, epg);
|
2008-04-16 01:56:35 +00:00
|
|
|
}
|
|
|
|
|
2012-11-19 18:22:34 +00:00
|
|
|
static int ep93xx_gpio_probe(struct platform_device *pdev)
|
2008-04-16 01:56:35 +00:00
|
|
|
{
|
2018-08-22 20:41:02 +00:00
|
|
|
struct ep93xx_gpio *epg;
|
2011-06-08 21:35:33 +00:00
|
|
|
int i;
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2019-06-17 16:49:17 +00:00
|
|
|
epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
|
2018-08-22 20:41:02 +00:00
|
|
|
if (!epg)
|
2011-06-08 21:35:33 +00:00
|
|
|
return -ENOMEM;
|
2008-04-16 01:56:35 +00:00
|
|
|
|
2019-06-17 16:49:17 +00:00
|
|
|
epg->base = devm_platform_ioremap_resource(pdev, 0);
|
2018-08-22 20:41:02 +00:00
|
|
|
if (IS_ERR(epg->base))
|
|
|
|
return PTR_ERR(epg->base);
|
2011-01-27 16:29:29 +00:00
|
|
|
|
2011-06-08 21:35:33 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
|
2018-08-22 20:41:02 +00:00
|
|
|
struct gpio_chip *gc = &epg->gc[i];
|
2011-06-08 21:35:33 +00:00
|
|
|
struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
|
2011-01-27 16:29:29 +00:00
|
|
|
|
2019-08-12 13:00:00 +00:00
|
|
|
if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
|
2011-06-08 21:35:33 +00:00
|
|
|
dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
|
2018-08-22 20:41:11 +00:00
|
|
|
bank->label);
|
2008-04-16 01:56:35 +00:00
|
|
|
}
|
|
|
|
|
2011-06-08 21:35:33 +00:00
|
|
|
return 0;
|
|
|
|
}
|
ARM: 6636/1: ep93xx: default multiplexed gpio ports to gpio mode
The EP93xx C and D GPIO ports are multiplexed with the Keypad Interface
peripheral. At power-up they default into non-GPIO mode with the Key
Matrix controller enabled so these ports are unusable for GPIO. Note
that the Keypad Interface peripheral is only available in the EP9307,
EP9312, and EP9315 processor variants.
The keypad support will clear the DeviceConfig bits appropriately to
enable the Keypad Interface when the driver is loaded. And, when the
driver is unloaded it will set the bits to return the ports to GPIO mode.
To make these ports available for GPIO after power-up on all EP93xx
processor variants, set the KEYS and GONK bits in the DeviceConfig
register.
Similarly, the E, G, and H ports are multiplexed with the IDE Interface
peripheral. At power-up these also default into non-GPIO mode. Note
that the IDE peripheral is only available in the EP9312 and EP9315
processor variants.
Since an IDE driver is not even available in mainline, set the EONIDE,
GONIDE, and HONIDE bits in the DeviceConfig register so that these
ports will be available for GPIO use after power-up.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-25 00:05:35 +00:00
|
|
|
|
2011-06-08 21:35:33 +00:00
|
|
|
static struct platform_driver ep93xx_gpio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "gpio-ep93xx",
|
|
|
|
},
|
|
|
|
.probe = ep93xx_gpio_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init ep93xx_gpio_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&ep93xx_gpio_driver);
|
2008-04-16 01:56:35 +00:00
|
|
|
}
|
2011-06-08 21:35:33 +00:00
|
|
|
postcore_initcall(ep93xx_gpio_init);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
|
|
|
|
"H Hartley Sweeten <hsweeten@visionengravers.com>");
|
|
|
|
MODULE_DESCRIPTION("EP93XX GPIO driver");
|
|
|
|
MODULE_LICENSE("GPL");
|