[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 19:14:41 +00:00
|
|
|
/*
|
2008-08-05 15:14:15 +00:00
|
|
|
* arch/arm/mach-orion5x/include/mach/system.h
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 19:14:41 +00:00
|
|
|
*
|
|
|
|
|
* Tzachi Perelstein <tzachi@marvell.com>
|
|
|
|
|
*
|
2008-03-27 18:51:41 +00:00
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 19:14:41 +00:00
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef __ASM_ARCH_SYSTEM_H
|
|
|
|
|
#define __ASM_ARCH_SYSTEM_H
|
|
|
|
|
|
2008-08-05 15:14:15 +00:00
|
|
|
#include <mach/hardware.h>
|
|
|
|
|
#include <mach/orion5x.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 19:14:41 +00:00
|
|
|
|
|
|
|
|
static inline void arch_idle(void)
|
|
|
|
|
{
|
|
|
|
|
cpu_do_idle();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void arch_reset(char mode)
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* Enable and issue soft reset
|
|
|
|
|
*/
|
2008-03-27 18:51:41 +00:00
|
|
|
orion5x_setbits(CPU_RESET_MASK, (1 << 2));
|
|
|
|
|
orion5x_setbits(CPU_SOFT_RESET, 1);
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 19:14:41 +00:00
|
|
|
}
|
|
|
|
|
|
2008-03-27 18:51:41 +00:00
|
|
|
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 19:14:41 +00:00
|
|
|
#endif
|
