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200 lines
5.1 KiB
C
200 lines
5.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <soc/tegra/common.h>
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#include "clk.h"
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/*
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* This driver manages performance state of the core power domain for the
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* independent PLLs and system clocks. We created a virtual clock device
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* for such clocks, see tegra_clk_dev_register().
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*/
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struct tegra_clk_device {
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struct notifier_block clk_nb;
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struct device *dev;
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struct clk_hw *hw;
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struct mutex lock;
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};
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static int tegra_clock_set_pd_state(struct tegra_clk_device *clk_dev,
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unsigned long rate)
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{
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struct device *dev = clk_dev->dev;
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struct dev_pm_opp *opp;
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unsigned int pstate;
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opp = dev_pm_opp_find_freq_ceil(dev, &rate);
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if (opp == ERR_PTR(-ERANGE)) {
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/*
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* Some clocks may be unused by a particular board and they
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* may have uninitiated clock rate that is overly high. In
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* this case clock is expected to be disabled, but still we
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* need to set up performance state of the power domain and
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* not error out clk initialization. A typical example is
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* a PCIe clock on Android tablets.
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*/
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dev_dbg(dev, "failed to find ceil OPP for %luHz\n", rate);
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opp = dev_pm_opp_find_freq_floor(dev, &rate);
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}
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if (IS_ERR(opp)) {
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dev_err(dev, "failed to find OPP for %luHz: %pe\n", rate, opp);
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return PTR_ERR(opp);
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}
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pstate = dev_pm_opp_get_required_pstate(opp, 0);
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dev_pm_opp_put(opp);
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return dev_pm_genpd_set_performance_state(dev, pstate);
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}
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static int tegra_clock_change_notify(struct notifier_block *nb,
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unsigned long msg, void *data)
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{
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struct clk_notifier_data *cnd = data;
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struct tegra_clk_device *clk_dev;
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int err = 0;
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clk_dev = container_of(nb, struct tegra_clk_device, clk_nb);
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mutex_lock(&clk_dev->lock);
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switch (msg) {
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case PRE_RATE_CHANGE:
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if (cnd->new_rate > cnd->old_rate)
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err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);
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break;
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case ABORT_RATE_CHANGE:
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err = tegra_clock_set_pd_state(clk_dev, cnd->old_rate);
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break;
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case POST_RATE_CHANGE:
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if (cnd->new_rate < cnd->old_rate)
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err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);
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break;
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default:
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break;
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}
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mutex_unlock(&clk_dev->lock);
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return notifier_from_errno(err);
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}
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static int tegra_clock_sync_pd_state(struct tegra_clk_device *clk_dev)
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{
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unsigned long rate;
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int ret;
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mutex_lock(&clk_dev->lock);
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rate = clk_hw_get_rate(clk_dev->hw);
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ret = tegra_clock_set_pd_state(clk_dev, rate);
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mutex_unlock(&clk_dev->lock);
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return ret;
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}
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static int tegra_clock_probe(struct platform_device *pdev)
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{
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struct tegra_core_opp_params opp_params = {};
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struct tegra_clk_device *clk_dev;
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struct device *dev = &pdev->dev;
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struct clk *clk;
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int err;
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if (!dev->pm_domain)
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return -EINVAL;
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clk_dev = devm_kzalloc(dev, sizeof(*clk_dev), GFP_KERNEL);
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if (!clk_dev)
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return -ENOMEM;
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clk_dev->dev = dev;
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clk_dev->hw = __clk_get_hw(clk);
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clk_dev->clk_nb.notifier_call = tegra_clock_change_notify;
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mutex_init(&clk_dev->lock);
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platform_set_drvdata(pdev, clk_dev);
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/*
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* Runtime PM was already enabled for this device by the parent clk
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* driver and power domain state should be synced under clk_dev lock,
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* hence we don't use the common OPP helper that initializes OPP
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* state. For some clocks common OPP helper may fail to find ceil
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* rate, it's handled by this driver.
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*/
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err = devm_tegra_core_dev_init_opp_table(dev, &opp_params);
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if (err)
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return err;
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err = clk_notifier_register(clk, &clk_dev->clk_nb);
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if (err) {
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dev_err(dev, "failed to register clk notifier: %d\n", err);
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return err;
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}
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/*
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* The driver is attaching to a potentially active/resumed clock, hence
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* we need to sync the power domain performance state in a accordance to
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* the clock rate if clock is resumed.
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*/
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err = tegra_clock_sync_pd_state(clk_dev);
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if (err)
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goto unreg_clk;
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return 0;
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unreg_clk:
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clk_notifier_unregister(clk, &clk_dev->clk_nb);
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return err;
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}
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/*
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* Tegra GENPD driver enables clocks during NOIRQ phase. It can't be done
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* for clocks served by this driver because runtime PM is unavailable in
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* NOIRQ phase. We will keep clocks resumed during suspend to mitigate this
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* problem. In practice this makes no difference from a power management
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* perspective since voltage is kept at a nominal level during suspend anyways.
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*/
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static const struct dev_pm_ops tegra_clock_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_resume_and_get, pm_runtime_put)
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};
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static const struct of_device_id tegra_clock_match[] = {
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{ .compatible = "nvidia,tegra20-sclk" },
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{ .compatible = "nvidia,tegra30-sclk" },
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{ .compatible = "nvidia,tegra30-pllc" },
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{ .compatible = "nvidia,tegra30-plle" },
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{ .compatible = "nvidia,tegra30-pllm" },
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{ }
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};
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static struct platform_driver tegra_clock_driver = {
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.driver = {
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.name = "tegra-clock",
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.of_match_table = tegra_clock_match,
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.pm = &tegra_clock_pm,
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.suppress_bind_attrs = true,
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},
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.probe = tegra_clock_probe,
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};
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builtin_platform_driver(tegra_clock_driver);
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