2005-04-16 22:20:36 +00:00
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/*
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* Copyright 2001-2002 Pavel Machek <pavel@suse.cz>
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* Based on code
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* Copyright 2001 Patrick Mochel <mochel@osdl.org>
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*/
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2008-10-23 05:26:29 +00:00
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#ifndef _ASM_X86_SUSPEND_32_H
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#define _ASM_X86_SUSPEND_32_H
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2008-06-10 21:45:45 +00:00
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2005-04-16 22:20:36 +00:00
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#include <asm/desc.h>
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2015-04-24 00:46:00 +00:00
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#include <asm/fpu/api.h>
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2005-04-16 22:20:36 +00:00
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/* image of the saved processor state */
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struct saved_context {
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2008-03-23 08:03:35 +00:00
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u16 es, fs, gs, ss;
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2005-04-16 22:20:36 +00:00
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unsigned long cr0, cr2, cr3, cr4;
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2010-06-07 22:32:49 +00:00
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u64 misc_enable;
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bool misc_enable_saved;
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x86/pm: Introduce quirk framework to save/restore extra MSR registers around suspend/resume
A bug was reported that on certain Broadwell platforms, after
resuming from S3, the CPU is running at an anomalously low
speed.
It turns out that the BIOS has modified the value of the
THERM_CONTROL register during S3, and changed it from 0 to 0x10,
thus enabled clock modulation(bit4), but with undefined CPU Duty
Cycle(bit1:3) - which causes the problem.
Here is a simple scenario to reproduce the issue:
1. Boot up the system
2. Get MSR 0x19a, it should be 0
3. Put the system into sleep, then wake it up
4. Get MSR 0x19a, it shows 0x10, while it should be 0
Although some BIOSen want to change the CPU Duty Cycle during
S3, in our case we don't want the BIOS to do any modification.
Fix this issue by introducing a more generic x86 framework to
save/restore specified MSR registers(THERM_CONTROL in this case)
for suspend/resume. This allows us to fix similar bugs in a much
simpler way in the future.
When the kernel wants to protect certain MSRs during suspending,
we simply add a quirk entry in msr_save_dmi_table, and customize
the MSR registers inside the quirk callback, for example:
u32 msr_id_need_to_save[] = {MSR_ID0, MSR_ID1, MSR_ID2...};
and the quirk mechanism ensures that, once resumed from suspend,
the MSRs indicated by these IDs will be restored to their
original, pre-suspend values.
Since both 64-bit and 32-bit kernels are affected, this patch
covers the common 64/32-bit suspend/resume code path. And
because the MSRs specified by the user might not be available or
readable in any situation, we use rdmsrl_safe() to safely save
these MSRs.
Reported-and-tested-by: Marcin Kaszewski <marcin.kaszewski@intel.com>
Signed-off-by: Chen Yu <yu.c.chen@intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: bp@suse.de
Cc: len.brown@intel.com
Cc: linux@horizon.com
Cc: luto@kernel.org
Cc: rjw@rjwysocki.net
Link: http://lkml.kernel.org/r/c9abdcbc173dd2f57e8990e304376f19287e92ba.1448382971.git.yu.c.chen@intel.com
[ More edits to the naming of data structures. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-11-24 17:03:41 +00:00
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struct saved_msrs saved_msrs;
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2013-05-02 01:53:30 +00:00
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struct desc_ptr gdt_desc;
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2008-01-30 12:31:12 +00:00
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struct desc_ptr idt;
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2005-04-16 22:20:36 +00:00
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u16 ldt;
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u16 tss;
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unsigned long tr;
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unsigned long safety;
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unsigned long return_address;
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} __attribute__((packed));
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2008-10-23 05:26:29 +00:00
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#endif /* _ASM_X86_SUSPEND_32_H */
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