linux/drivers/clk/nuvoton/Kconfig

# SPDX-License-Identifier: GPL-2.0
# common clock support for Nuvoton SoC family.

config COMMON_CLK_NUVOTON
	bool "Nuvoton clock controller common support"
	depends on ARCH_MA35 || COMPILE_TEST
	default y
	help
	  Say y here to enable common clock controller for Nuvoton platforms.

if COMMON_CLK_NUVOTON

config CLK_MA35D1
	bool "Nuvoton MA35D1 clock controller support"
	default y
	help
	  Build the clock controller driver for MA35D1 SoC.

endif
clk: nuvoton: Add clock driver for ma35d1 clock controller The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. This driver support ma35d1 clock gating, divider, and individual PLL configuration. There are 6 PLLs in ma35d1 SoC: - CA-PLL for the two Cortex-A35 CPU clock - SYS-PLL for system bus, which comes from the companion MCU and cannot be programmed by clock controller. - DDR-PLL for DDR - EPLL for GMAC and GFX, Display, and VDEC IPs. - VPLL for video output pixel clock - APLL for SDHC, I2S audio, and other IPs. CA-PLL has only one operation mode. DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 operation modes: integer mode, fraction mode, and spread specturm mode. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2023-06-05 04:07:47 +00:00			`# SPDX-License-Identifier: GPL-2.0`
			`# common clock support for Nuvoton SoC family.`

			`config COMMON_CLK_NUVOTON`
			`bool "Nuvoton clock controller common support"`
			`depends on ARCH_MA35 \|\| COMPILE_TEST`
			`default y`
			`help`
			`Say y here to enable common clock controller for Nuvoton platforms.`

			`if COMMON_CLK_NUVOTON`

			`config CLK_MA35D1`
			`bool "Nuvoton MA35D1 clock controller support"`
			`default y`
			`help`
			`Build the clock controller driver for MA35D1 SoC.`

			`endif`