2014-11-26 05:44:37 +00:00
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* USB2 ChipIdea USB controller for ci13xxx
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Required properties:
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2015-05-29 16:38:44 +00:00
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- compatible: should be one of:
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"fsl,imx27-usb"
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"lsi,zevio-usb"
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"qcom,ci-hdrc"
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"chipidea,usb2"
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2014-11-26 05:44:37 +00:00
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- reg: base address and length of the registers
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- interrupts: interrupt for the USB controller
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2015-05-29 16:38:44 +00:00
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Recommended properies:
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- phy_type: the type of the phy connected to the core. Should be one
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of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
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property the PORTSC register won't be touched.
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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Deprecated properties:
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- usb-phy: phandle for the PHY device. Use "phys" instead.
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- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
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2014-11-26 05:44:37 +00:00
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Optional properties:
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- clocks: reference to the USB clock
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- phys: reference to the USB PHY
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- phy-names: should be "usb-phy"
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- vbus-supply: reference to the VBUS regulator
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2015-05-29 16:38:44 +00:00
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- maximum-speed: limit the maximum connection speed to "full-speed".
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- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
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- fsl,usbmisc: (FSL only) phandler of non-core register device, with one
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argument that indicate usb controller index
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- disable-over-current: (FSL only) disable over current detect
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- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
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2015-07-15 05:53:05 +00:00
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- itc-setting: interrupt threshold control register control, the setting
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should be aligned with ITC bits at register USBCMD.
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2014-11-26 05:44:37 +00:00
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Example:
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usb@f7ed0000 {
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compatible = "chipidea,usb2";
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reg = <0xf7ed0000 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_USB0>;
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phys = <&usb_phy0>;
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phy-names = "usb-phy";
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vbus-supply = <®_usb0_vbus>;
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2015-07-15 05:53:05 +00:00
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gadget-itc-setting = <0x4>; /* 4 micro-frames */
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2014-11-26 05:44:37 +00:00
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};
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