2011-12-12 18:31:55 +00:00
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/*
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* arch/arm/include/asm/opcodes.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_OPCODES_H
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#define __ASM_ARM_OPCODES_H
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#ifndef __ASSEMBLY__
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extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
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#endif
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#define ARM_OPCODE_CONDTEST_FAIL 0
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#define ARM_OPCODE_CONDTEST_PASS 1
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#define ARM_OPCODE_CONDTEST_UNCOND 2
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2012-02-01 09:42:22 +00:00
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2012-09-03 12:49:23 +00:00
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/*
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* Assembler opcode byteswap helpers.
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* These are only intended for use by this header: don't use them directly,
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* because they will be suboptimal in most cases.
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*/
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#define ___asm_opcode_swab32(x) ( \
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(((x) << 24) & 0xFF000000) \
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| (((x) << 8) & 0x00FF0000) \
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| (((x) >> 8) & 0x0000FF00) \
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| (((x) >> 24) & 0x000000FF) \
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)
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#define ___asm_opcode_swab16(x) ( \
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(((x) << 8) & 0xFF00) \
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| (((x) >> 8) & 0x00FF) \
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)
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#define ___asm_opcode_swahb32(x) ( \
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(((x) << 8) & 0xFF00FF00) \
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| (((x) >> 8) & 0x00FF00FF) \
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)
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#define ___asm_opcode_swahw32(x) ( \
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(((x) << 16) & 0xFFFF0000) \
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| (((x) >> 16) & 0x0000FFFF) \
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)
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#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
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#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
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2012-02-01 09:42:22 +00:00
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/*
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* Opcode byteswap helpers
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*
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* These macros help with converting instructions between a canonical integer
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* format and in-memory representation, in an endianness-agnostic manner.
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*
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* __mem_to_opcode_*() convert from in-memory representation to canonical form.
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* __opcode_to_mem_*() convert from canonical form to in-memory representation.
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*
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*
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* Canonical instruction representation:
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*
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* ARM: 0xKKLLMMNN
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* Thumb 16-bit: 0x0000KKLL, where KK < 0xE8
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* Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8
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*
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* There is no way to distinguish an ARM instruction in canonical representation
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* from a Thumb instruction (just as these cannot be distinguished in memory).
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* Where this distinction is important, it needs to be tracked separately.
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*
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* Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
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* represent any valid Thumb-2 instruction. For this range,
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* __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
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2012-09-03 12:49:23 +00:00
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*
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* The ___asm variants are intended only for use by this header, in situations
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* involving inline assembler. For .S files, the normal __opcode_*() macros
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* should do the right thing.
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2012-02-01 09:42:22 +00:00
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*/
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2012-09-03 12:49:23 +00:00
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#ifdef __ASSEMBLY__
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2012-02-01 09:42:22 +00:00
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2012-09-03 12:49:23 +00:00
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#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
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#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
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#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
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#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
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#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
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#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
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#else /* ! __ASSEMBLY__ */
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2012-02-01 09:42:22 +00:00
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#include <linux/types.h>
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#include <linux/swab.h>
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2012-09-03 12:49:23 +00:00
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#define ___opcode_swab32(x) swab32(x)
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#define ___opcode_swab16(x) swab16(x)
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#define ___opcode_swahb32(x) swahb32(x)
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#define ___opcode_swahw32(x) swahw32(x)
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#define ___opcode_identity32(x) ((u32)(x))
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#define ___opcode_identity16(x) ((u16)(x))
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#endif /* ! __ASSEMBLY__ */
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2012-02-01 09:42:22 +00:00
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#ifdef CONFIG_CPU_ENDIAN_BE8
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2012-09-03 12:49:22 +00:00
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2012-09-03 12:49:23 +00:00
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#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
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#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
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#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
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#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
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#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
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#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
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2012-09-03 12:49:22 +00:00
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#else /* ! CONFIG_CPU_ENDIAN_BE8 */
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2012-09-03 12:49:23 +00:00
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#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
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#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
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#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
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#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
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2012-09-03 12:49:22 +00:00
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#ifndef CONFIG_CPU_ENDIAN_BE32
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/*
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* On BE32 systems, using 32-bit accesses to store Thumb instructions will not
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* work in all cases, due to alignment constraints. For now, a correct
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* version is not provided for BE32.
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*/
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2012-09-03 12:49:23 +00:00
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#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
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#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
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2012-02-01 09:42:22 +00:00
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#endif
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2012-09-03 12:49:22 +00:00
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#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
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2012-02-01 09:42:22 +00:00
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#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
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#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
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2012-09-03 12:49:22 +00:00
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#ifndef CONFIG_CPU_ENDIAN_BE32
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2012-02-01 09:42:22 +00:00
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#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
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2012-09-03 12:49:22 +00:00
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#endif
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2012-02-01 09:42:22 +00:00
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/* Operations specific to Thumb opcodes */
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/* Instruction size checks: */
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2012-09-03 12:49:23 +00:00
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#define __opcode_is_thumb32(x) ( \
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((x) & 0xF8000000) == 0xE8000000 \
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|| ((x) & 0xF0000000) == 0xF0000000 \
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)
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#define __opcode_is_thumb16(x) ( \
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((x) & 0xFFFF0000) == 0 \
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&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000) \
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)
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2012-02-01 09:42:22 +00:00
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/* Operations to construct or split 32-bit Thumb instructions: */
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2012-09-03 12:49:23 +00:00
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#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
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#define __opcode_thumb32_second(x) (___opcode_identity16(x))
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#define __opcode_thumb32_compose(first, second) ( \
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(___opcode_identity32(___opcode_identity16(first)) << 16) \
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| ___opcode_identity32(___opcode_identity16(second)) \
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)
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#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
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#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
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#define ___asm_opcode_thumb32_compose(first, second) ( \
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(___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
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| ___asm_opcode_identity32(___asm_opcode_identity16(second)) \
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)
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2012-02-01 09:42:22 +00:00
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2011-12-12 18:31:55 +00:00
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#endif /* __ASM_ARM_OPCODES_H */
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