2005-04-16 22:20:36 +00:00
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/*
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2008-08-02 09:55:55 +00:00
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* arch/arm/include/asm/cacheflush.h
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2005-04-16 22:20:36 +00:00
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*
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* Copyright (C) 1999-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_CACHEFLUSH_H
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#define _ASMARM_CACHEFLUSH_H
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#include <linux/mm.h>
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2011-02-06 15:32:24 +00:00
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#include <asm/glue-cache.h>
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2005-06-20 10:31:09 +00:00
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#include <asm/shmparam.h>
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2008-11-06 13:23:08 +00:00
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#include <asm/cachetype.h>
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2010-03-24 15:46:52 +00:00
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#include <asm/outercache.h>
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2005-06-20 10:31:09 +00:00
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#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
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2005-04-16 22:20:36 +00:00
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/*
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2010-09-13 14:57:36 +00:00
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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2005-04-16 22:20:36 +00:00
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*/
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2010-09-13 14:57:36 +00:00
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#define PG_dcache_clean PG_arch_1
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2005-04-16 22:20:36 +00:00
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
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* implement these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive;
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* start addresses should be rounded down, end addresses up.
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*
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2018-05-08 18:14:57 +00:00
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* See Documentation/core-api/cachetlb.rst for more information.
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2005-04-16 22:20:36 +00:00
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* Please note that the implementation of these, and the required
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* effects are cache-type (VIVT/VIPT/PIPT) specific.
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*
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2010-09-21 16:16:40 +00:00
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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* Currently only needed for cache-v6.S and cache-v7.S, see
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* __flush_icache_all for the generic implementation.
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*
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2010-01-19 22:42:08 +00:00
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* flush_kern_all()
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2005-04-16 22:20:36 +00:00
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*
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* Unconditionally clean and invalidate the entire cache.
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*
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2012-09-06 13:05:13 +00:00
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* flush_kern_louis()
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*
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* Flush data cache levels up to the level of unification
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* inner shareable and invalidate the I-cache.
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* Only needed from v7 onwards, falls back to flush_cache_all()
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* for all other processor versions.
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*
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2010-01-19 22:42:08 +00:00
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* flush_user_all()
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2005-04-16 22:20:36 +00:00
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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2010-01-19 22:42:08 +00:00
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* flush_user_range(start, end, flags)
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2005-04-16 22:20:36 +00:00
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*
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* Clean and invalidate a range of cache entries in the
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* specified address space before a change of page tables.
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* - start - user start address (inclusive, page aligned)
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* - end - user end address (exclusive, page aligned)
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* - flags - vma->vm_flags field
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*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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2010-01-19 22:42:08 +00:00
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* flush_kern_dcache_area(kaddr, size)
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*
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* Ensure that the data held in page is written back.
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* - kaddr - page address
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* - size - region size
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*
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2005-04-16 22:20:36 +00:00
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* DMA Cache Coherency
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* ===================
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*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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* - start - virtual start address
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* - end - virtual end address
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*/
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struct cpu_cache_fns {
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2010-09-21 16:16:40 +00:00
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void (*flush_icache_all)(void);
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2005-04-16 22:20:36 +00:00
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void (*flush_kern_all)(void);
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2012-09-06 13:05:13 +00:00
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void (*flush_kern_louis)(void);
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2005-04-16 22:20:36 +00:00
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void (*flush_user_all)(void);
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void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
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void (*coherent_kern_range)(unsigned long, unsigned long);
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2012-04-27 12:08:53 +00:00
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int (*coherent_user_range)(unsigned long, unsigned long);
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2009-11-26 12:56:21 +00:00
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void (*flush_kern_dcache_area)(void *, size_t);
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2005-04-16 22:20:36 +00:00
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2009-11-26 16:19:58 +00:00
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void (*dma_map_area)(const void *, size_t, int);
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void (*dma_unmap_area)(const void *, size_t, int);
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2005-04-16 22:20:36 +00:00
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2007-02-06 17:39:31 +00:00
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void (*dma_flush_range)(const void *, const void *);
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2016-10-28 07:45:16 +00:00
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} __no_randomize_layout;
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2005-04-16 22:20:36 +00:00
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/*
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* Select the calling method
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*/
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#ifdef MULTI_CACHE
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extern struct cpu_cache_fns cpu_cache;
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2010-09-21 16:16:40 +00:00
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#define __cpuc_flush_icache_all cpu_cache.flush_icache_all
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2005-04-16 22:20:36 +00:00
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#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
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2012-09-06 13:05:13 +00:00
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#define __cpuc_flush_kern_louis cpu_cache.flush_kern_louis
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2005-04-16 22:20:36 +00:00
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#define __cpuc_flush_user_all cpu_cache.flush_user_all
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#define __cpuc_flush_user_range cpu_cache.flush_user_range
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#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
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#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
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2009-11-26 12:56:21 +00:00
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#define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
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2005-04-16 22:20:36 +00:00
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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#define dmac_flush_range cpu_cache.dma_flush_range
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#else
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2010-09-21 16:16:40 +00:00
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extern void __cpuc_flush_icache_all(void);
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2005-04-16 22:20:36 +00:00
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extern void __cpuc_flush_kern_all(void);
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2012-09-06 13:05:13 +00:00
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extern void __cpuc_flush_kern_louis(void);
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2005-04-16 22:20:36 +00:00
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extern void __cpuc_flush_user_all(void);
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extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
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extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
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2012-04-27 12:08:53 +00:00
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extern int __cpuc_coherent_user_range(unsigned long, unsigned long);
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2009-11-26 12:56:21 +00:00
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extern void __cpuc_flush_dcache_area(void *, size_t);
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2005-04-16 22:20:36 +00:00
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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2007-02-06 17:39:31 +00:00
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extern void dmac_flush_range(const void *, const void *);
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2005-04-16 22:20:36 +00:00
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#endif
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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2009-11-05 13:29:36 +00:00
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extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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unsigned long, void *, const void *, unsigned long);
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2005-04-16 22:20:36 +00:00
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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} while (0)
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/*
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* Convert calls to our calling convention.
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*/
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2010-09-21 16:16:40 +00:00
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/* Invalidate I-cache */
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#define __flush_icache_all_generic() \
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asm("mcr p15, 0, %0, c7, c5, 0" \
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: : "r" (0));
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/* Invalidate I-cache inner shareable */
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#define __flush_icache_all_v7_smp() \
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asm("mcr p15, 0, %0, c7, c1, 0" \
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: : "r" (0));
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/*
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* Optimized __flush_icache_all for the common cases. Note that UP ARMv7
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* will fall through to use __flush_icache_all_generic.
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*/
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2011-01-17 15:08:32 +00:00
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#if (defined(CONFIG_CPU_V7) && \
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(defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
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2010-09-21 16:16:40 +00:00
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defined(CONFIG_SMP_ON_UP)
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#define __flush_icache_preferred __cpuc_flush_icache_all
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#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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#define __flush_icache_preferred __flush_icache_all_v7_smp
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#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
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#define __flush_icache_preferred __cpuc_flush_icache_all
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#else
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#define __flush_icache_preferred __flush_icache_all_generic
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#endif
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static inline void __flush_icache_all(void)
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{
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__flush_icache_preferred();
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2014-05-09 17:36:27 +00:00
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dsb(ishst);
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2010-09-21 16:16:40 +00:00
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}
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2012-09-06 13:05:13 +00:00
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/*
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* Flush caches up to Level of Unification Inner Shareable
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*/
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#define flush_cache_louis() __cpuc_flush_kern_louis()
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2005-04-16 22:20:36 +00:00
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#define flush_cache_all() __cpuc_flush_kern_all()
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2009-10-25 10:40:02 +00:00
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static inline void vivt_flush_cache_mm(struct mm_struct *mm)
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2005-04-16 22:20:36 +00:00
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{
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2009-09-24 15:34:49 +00:00
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
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2005-04-16 22:20:36 +00:00
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__cpuc_flush_user_all();
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}
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static inline void
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2009-10-25 10:40:02 +00:00
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vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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2005-04-16 22:20:36 +00:00
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{
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2012-07-23 13:18:13 +00:00
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struct mm_struct *mm = vma->vm_mm;
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if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
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2005-04-16 22:20:36 +00:00
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__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
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vma->vm_flags);
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}
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static inline void
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2009-10-25 10:40:02 +00:00
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vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
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2005-04-16 22:20:36 +00:00
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{
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2012-07-23 13:18:13 +00:00
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struct mm_struct *mm = vma->vm_mm;
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if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
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2005-04-16 22:20:36 +00:00
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unsigned long addr = user_addr & PAGE_MASK;
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__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
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}
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}
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2006-09-02 17:43:20 +00:00
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2009-10-25 10:40:02 +00:00
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#ifndef CONFIG_CPU_CACHE_VIPT
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#define flush_cache_mm(mm) \
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vivt_flush_cache_mm(mm)
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#define flush_cache_range(vma,start,end) \
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vivt_flush_cache_range(vma,start,end)
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#define flush_cache_page(vma,addr,pfn) \
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vivt_flush_cache_page(vma,addr,pfn)
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2005-09-08 14:32:23 +00:00
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#else
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extern void flush_cache_mm(struct mm_struct *mm);
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extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
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extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
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#endif
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2005-04-16 22:20:36 +00:00
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2006-12-12 17:14:57 +00:00
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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2005-04-16 22:20:36 +00:00
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/*
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* flush_cache_user_range is used when we want to ensure that the
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* Harvard caches are synchronised for the user space address range.
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* This is used for the ARM private sys_cacheflush system call.
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*/
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2012-08-21 14:33:19 +00:00
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#define flush_cache_user_range(s,e) __cpuc_coherent_user_range(s,e)
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2005-04-16 22:20:36 +00:00
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/*
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* Perform necessary cache operations to ensure that data previously
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* stored within this range of addresses can be executed by the CPU.
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*/
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#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
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/*
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* Perform necessary cache operations to ensure that the TLB will
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* see data written in the specified area.
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*/
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#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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2009-11-26 08:16:19 +00:00
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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2005-04-16 22:20:36 +00:00
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extern void flush_dcache_page(struct page *);
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2010-01-25 17:42:22 +00:00
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static inline void flush_kernel_vmap_range(void *addr, int size)
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|
{
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|
|
if ((cache_is_vivt() || cache_is_vipt_aliasing()))
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|
__cpuc_flush_dcache_area(addr, (size_t)size);
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|
}
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|
static inline void invalidate_kernel_vmap_range(void *addr, int size)
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|
|
|
{
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|
if ((cache_is_vivt() || cache_is_vipt_aliasing()))
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|
|
__cpuc_flush_dcache_area(addr, (size_t)size);
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|
}
|
2008-06-13 09:28:36 +00:00
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2006-12-30 23:17:40 +00:00
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#define ARCH_HAS_FLUSH_ANON_PAGE
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static inline void flush_anon_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vmaddr)
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|
{
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|
extern void __flush_anon_page(struct vm_area_struct *vma,
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|
struct page *, unsigned long);
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|
if (PageAnon(page))
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__flush_anon_page(vma, page, vmaddr);
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}
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|
2009-06-12 02:09:29 +00:00
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#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
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2013-06-10 20:10:12 +00:00
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extern void flush_kernel_dcache_page(struct page *);
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2009-06-12 02:09:29 +00:00
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2018-04-10 23:36:56 +00:00
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#define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages)
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#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages)
|
2005-04-16 22:20:36 +00:00
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|
#define flush_icache_user_range(vma,page,addr,len) \
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flush_dcache_page(page)
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|
/*
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* We don't appear to need to do anything here. In fact, if we did, we'd
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|
* duplicate cache flushing elsewhere performed by flush_dcache_page().
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*/
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|
#define flush_icache_page(vma,page) do { } while (0)
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|
2008-11-06 13:23:08 +00:00
|
|
|
/*
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|
|
* flush_cache_vmap() is used when creating mappings (eg, via vmap,
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|
|
* vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
|
|
|
|
* caches, since the direct-mappings of these pages may contain cached
|
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|
|
* data, we need to do a full cache flush to ensure that writebacks
|
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|
|
* don't corrupt data placed into these pages via the new mappings.
|
|
|
|
*/
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|
|
static inline void flush_cache_vmap(unsigned long start, unsigned long end)
|
|
|
|
{
|
|
|
|
if (!cache_is_vipt_nonaliasing())
|
|
|
|
flush_cache_all();
|
|
|
|
else
|
|
|
|
/*
|
|
|
|
* set_pte_at() called from vmap_pte_range() does not
|
|
|
|
* have a DSB after cleaning the cache line.
|
|
|
|
*/
|
2013-06-12 09:03:30 +00:00
|
|
|
dsb(ishst);
|
2008-11-06 13:23:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
|
|
|
|
{
|
|
|
|
if (!cache_is_vipt_nonaliasing())
|
|
|
|
flush_cache_all();
|
|
|
|
}
|
|
|
|
|
2013-04-23 20:45:40 +00:00
|
|
|
/*
|
|
|
|
* Memory synchronization helpers for mixed cached vs non cached accesses.
|
|
|
|
*
|
|
|
|
* Some synchronization algorithms have to set states in memory with the
|
|
|
|
* cache enabled or disabled depending on the code path. It is crucial
|
|
|
|
* to always ensure proper cache maintenance to update main memory right
|
|
|
|
* away in that case.
|
|
|
|
*
|
|
|
|
* Any cached write must be followed by a cache clean operation.
|
|
|
|
* Any cached read must be preceded by a cache invalidate operation.
|
|
|
|
* Yet, in the read case, a cache flush i.e. atomic clean+invalidate
|
|
|
|
* operation is needed to avoid discarding possible concurrent writes to the
|
|
|
|
* accessed memory.
|
|
|
|
*
|
|
|
|
* Also, in order to prevent a cached writer from interfering with an
|
|
|
|
* adjacent non-cached writer, each state variable must be located to
|
|
|
|
* a separate cache line.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This needs to be >= the max cache writeback size of all
|
|
|
|
* supported platforms included in the current kernel configuration.
|
|
|
|
* This is used to align state variables to their own cache lines.
|
|
|
|
*/
|
|
|
|
#define __CACHE_WRITEBACK_ORDER 6 /* guessed from existing platforms */
|
|
|
|
#define __CACHE_WRITEBACK_GRANULE (1 << __CACHE_WRITEBACK_ORDER)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There is no __cpuc_clean_dcache_area but we use it anyway for
|
|
|
|
* code intent clarity, and alias it to __cpuc_flush_dcache_area.
|
|
|
|
*/
|
|
|
|
#define __cpuc_clean_dcache_area __cpuc_flush_dcache_area
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ensure preceding writes to *p by this CPU are visible to
|
|
|
|
* subsequent reads by other CPUs:
|
|
|
|
*/
|
|
|
|
static inline void __sync_cache_range_w(volatile void *p, size_t size)
|
|
|
|
{
|
|
|
|
char *_p = (char *)p;
|
|
|
|
|
|
|
|
__cpuc_clean_dcache_area(_p, size);
|
|
|
|
outer_clean_range(__pa(_p), __pa(_p + size));
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ensure preceding writes to *p by other CPUs are visible to
|
|
|
|
* subsequent reads by this CPU. We must be careful not to
|
|
|
|
* discard data simultaneously written by another CPU, hence the
|
|
|
|
* usage of flush rather than invalidate operations.
|
|
|
|
*/
|
|
|
|
static inline void __sync_cache_range_r(volatile void *p, size_t size)
|
|
|
|
{
|
|
|
|
char *_p = (char *)p;
|
|
|
|
|
|
|
|
#ifdef CONFIG_OUTER_CACHE
|
|
|
|
if (outer_cache.flush_range) {
|
|
|
|
/*
|
|
|
|
* Ensure dirty data migrated from other CPUs into our cache
|
|
|
|
* are cleaned out safely before the outer cache is cleaned:
|
|
|
|
*/
|
|
|
|
__cpuc_clean_dcache_area(_p, size);
|
|
|
|
|
|
|
|
/* Clean and invalidate stale data for *p from outer ... */
|
|
|
|
outer_flush_range(__pa(_p), __pa(_p + size));
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* ... and inner cache: */
|
|
|
|
__cpuc_flush_dcache_area(_p, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
|
|
|
|
#define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
|
|
|
|
|
2013-10-18 21:06:03 +00:00
|
|
|
/*
|
|
|
|
* Disabling cache access for one CPU in an ARMv7 SMP system is tricky.
|
|
|
|
* To do so we must:
|
|
|
|
*
|
|
|
|
* - Clear the SCTLR.C bit to prevent further cache allocations
|
|
|
|
* - Flush the desired level of cache
|
|
|
|
* - Clear the ACTLR "SMP" bit to disable local coherency
|
|
|
|
*
|
|
|
|
* ... and so without any intervening memory access in between those steps,
|
|
|
|
* not even to the stack.
|
|
|
|
*
|
|
|
|
* WARNING -- After this has been called:
|
|
|
|
*
|
|
|
|
* - No ldrex/strex (and similar) instructions must be used.
|
|
|
|
* - The CPU is obviously no longer coherent with the other CPUs.
|
|
|
|
* - This is unlikely to work as expected if Linux is running non-secure.
|
|
|
|
*
|
|
|
|
* Note:
|
|
|
|
*
|
|
|
|
* - This is known to apply to several ARMv7 processor implementations,
|
|
|
|
* however some exceptions may exist. Caveat emptor.
|
|
|
|
*
|
|
|
|
* - The clobber list is dictated by the call to v7_flush_dcache_*.
|
|
|
|
* fp is preserved to the stack explicitly prior disabling the cache
|
|
|
|
* since adding it to the clobber list is incompatible with having
|
|
|
|
* CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering
|
|
|
|
* trampoline are inserted by the linker and to keep sp 64-bit aligned.
|
|
|
|
*/
|
|
|
|
#define v7_exit_coherency_flush(level) \
|
|
|
|
asm volatile( \
|
2014-09-28 04:36:46 +00:00
|
|
|
".arch armv7-a \n\t" \
|
2013-10-18 21:06:03 +00:00
|
|
|
"stmfd sp!, {fp, ip} \n\t" \
|
|
|
|
"mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
|
|
|
|
"bic r0, r0, #"__stringify(CR_C)" \n\t" \
|
|
|
|
"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
|
|
|
|
"isb \n\t" \
|
|
|
|
"bl v7_flush_dcache_"__stringify(level)" \n\t" \
|
|
|
|
"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
|
|
|
|
"bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
|
|
|
|
"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
|
|
|
|
"isb \n\t" \
|
|
|
|
"dsb \n\t" \
|
|
|
|
"ldmfd sp!, {fp, ip}" \
|
|
|
|
: : : "r0","r1","r2","r3","r4","r5","r6","r7", \
|
|
|
|
"r9","r10","lr","memory" )
|
|
|
|
|
2014-04-29 03:20:52 +00:00
|
|
|
void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
|
|
|
|
void *kaddr, unsigned long len);
|
2014-04-03 20:29:50 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
#endif
|