2019-07-23 10:12:47 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2019-06-28 12:51:43 +00:00
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/*
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2019-07-23 10:12:47 +00:00
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* rt1308.h -- RT1308 ALSA SoC amplifier component driver
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2019-06-28 12:51:43 +00:00
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*
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* Copyright 2019 Realtek Semiconductor Corp.
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* Author: Derek Fang <derek.fang@realtek.com>
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*
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*/
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#ifndef _RT1308_H_
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#define _RT1308_H_
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#define RT1308_DEVICE_ID_NUM 0x10ec1300
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#define RT1308_RESET 0x00
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#define RT1308_RESET_N 0x01
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#define RT1308_CLK_GATING 0x02
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#define RT1308_PLL_1 0x03
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#define RT1308_PLL_2 0x04
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#define RT1308_PLL_INT 0x05
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#define RT1308_CLK_1 0x06
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#define RT1308_DATA_PATH 0x07
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#define RT1308_CLK_2 0x08
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#define RT1308_SIL_DET 0x09
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#define RT1308_CLK_DET 0x0a
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#define RT1308_DC_DET 0x0b
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#define RT1308_DC_DET_THRES 0x0c
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#define RT1308_DAC_SET 0x10
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#define RT1308_SRC_SET 0x11
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#define RT1308_DAC_BUF 0x12
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#define RT1308_ADC_SET 0x13
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#define RT1308_ADC_SET_INT 0x14
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#define RT1308_I2S_SET_1 0x15
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#define RT1308_I2S_SET_2 0x16
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#define RT1308_I2C_I2S_SDW_SET 0x17
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#define RT1308_SDW_REG_RW 0x18
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#define RT1308_SDW_REG_RDATA 0x19
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#define RT1308_IV_SENSE 0x1a
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#define RT1308_I2S_TX_DAC_SET 0x1b
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#define RT1308_AD_FILTER_SET 0x1c
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#define RT1308_DC_CAL_1 0x20
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#define RT1308_DC_CAL_2 0x21
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#define RT1308_DC_CAL_L_OFFSET 0x22
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#define RT1308_DC_CAL_R_OFFSET 0x23
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#define RT1308_PVDD_OFFSET_CTL 0x24
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#define RT1308_PVDD_OFFSET_L 0x25
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#define RT1308_PVDD_OFFSET_R 0x26
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#define RT1308_PVDD_OFFSET_PBTL 0x27
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#define RT1308_PVDD_OFFSET_PVDD 0x28
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#define RT1308_CAL_OFFSET_DAC_PBTL 0x29
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#define RT1308_CAL_OFFSET_DAC_L 0x2a
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#define RT1308_CAL_OFFSET_DAC_R 0x2b
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#define RT1308_CAL_OFFSET_PWM_L 0x2c
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#define RT1308_CAL_OFFSET_PWM_R 0x2d
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#define RT1308_CAL_PWM_VOS_ADC_L 0x2e
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#define RT1308_CAL_PWM_VOS_ADC_R 0x2f
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#define RT1308_CLASS_D_SET_1 0x30
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#define RT1308_CLASS_D_SET_2 0x31
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#define RT1308_POWER 0x32
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#define RT1308_LDO 0x33
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#define RT1308_VREF 0x34
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#define RT1308_MBIAS 0x35
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#define RT1308_POWER_STATUS 0x36
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#define RT1308_POWER_INT 0x37
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#define RT1308_SINE_TONE_GEN_1 0x50
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#define RT1308_SINE_TONE_GEN_2 0x51
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#define RT1308_BQ_SET 0x54
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#define RT1308_BQ_PARA_UPDATE 0x55
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#define RT1308_BQ_PRE_VOL_L 0x56
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#define RT1308_BQ_PRE_VOL_R 0x57
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#define RT1308_BQ_POST_VOL_L 0x58
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#define RT1308_BQ_POST_VOL_R 0x59
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#define RT1308_BQ1_L_H0 0x5b
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#define RT1308_BQ1_L_B1 0x5c
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#define RT1308_BQ1_L_B2 0x5d
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#define RT1308_BQ1_L_A1 0x5e
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#define RT1308_BQ1_L_A2 0x5f
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#define RT1308_BQ1_R_H0 0x60
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#define RT1308_BQ1_R_B1 0x61
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#define RT1308_BQ1_R_B2 0x62
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#define RT1308_BQ1_R_A1 0x63
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#define RT1308_BQ1_R_A2 0x64
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#define RT1308_BQ2_L_H0 0x65
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#define RT1308_BQ2_L_B1 0x66
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#define RT1308_BQ2_L_B2 0x67
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#define RT1308_BQ2_L_A1 0x68
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#define RT1308_BQ2_L_A2 0x69
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#define RT1308_BQ2_R_H0 0x6a
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#define RT1308_BQ2_R_B1 0x6b
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#define RT1308_BQ2_R_B2 0x6c
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#define RT1308_BQ2_R_A1 0x6d
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#define RT1308_BQ2_R_A2 0x6e
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#define RT1308_VEN_DEV_ID 0x70
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#define RT1308_VERSION_ID 0x71
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#define RT1308_SPK_BOUND 0x72
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#define RT1308_BQ1_EQ_L_1 0x73
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#define RT1308_BQ1_EQ_L_2 0x74
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#define RT1308_BQ1_EQ_L_3 0x75
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#define RT1308_BQ1_EQ_R_1 0x76
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#define RT1308_BQ1_EQ_R_2 0x77
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#define RT1308_BQ1_EQ_R_3 0x78
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#define RT1308_BQ2_EQ_L_1 0x79
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#define RT1308_BQ2_EQ_L_2 0x7a
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#define RT1308_BQ2_EQ_L_3 0x7b
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#define RT1308_BQ2_EQ_R_1 0x7c
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#define RT1308_BQ2_EQ_R_2 0x7d
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#define RT1308_BQ2_EQ_R_3 0x7e
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#define RT1308_EFUSE_1 0x7f
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#define RT1308_EFUSE_2 0x80
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#define RT1308_EFUSE_PROG_PVDD_L 0x81
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#define RT1308_EFUSE_PROG_PVDD_R 0x82
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#define RT1308_EFUSE_PROG_R0_L 0x83
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#define RT1308_EFUSE_PROG_R0_R 0x84
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#define RT1308_EFUSE_PROG_DEV 0x85
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#define RT1308_EFUSE_READ_PVDD_L 0x86
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#define RT1308_EFUSE_READ_PVDD_R 0x87
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#define RT1308_EFUSE_READ_PVDD_PTBL 0x88
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#define RT1308_EFUSE_READ_DEV 0x89
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#define RT1308_EFUSE_READ_R0 0x8a
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#define RT1308_EFUSE_READ_ADC_L 0x8b
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#define RT1308_EFUSE_READ_ADC_R 0x8c
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#define RT1308_EFUSE_READ_ADC_PBTL 0x8d
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#define RT1308_EFUSE_RESERVE 0x8e
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#define RT1308_PADS_1 0x90
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#define RT1308_PADS_2 0x91
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#define RT1308_TEST_MODE 0xa0
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#define RT1308_TEST_1 0xa1
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#define RT1308_TEST_2 0xa2
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#define RT1308_TEST_3 0xa3
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#define RT1308_TEST_4 0xa4
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#define RT1308_EFUSE_DATA_0_MSB 0xb0
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#define RT1308_EFUSE_DATA_0_LSB 0xb1
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#define RT1308_EFUSE_DATA_1_MSB 0xb2
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#define RT1308_EFUSE_DATA_1_LSB 0xb3
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#define RT1308_EFUSE_DATA_2_MSB 0xb4
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#define RT1308_EFUSE_DATA_2_LSB 0xb5
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#define RT1308_EFUSE_DATA_3_MSB 0xb6
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#define RT1308_EFUSE_DATA_3_LSB 0xb7
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#define RT1308_EFUSE_DATA_TEST_MSB 0xb8
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#define RT1308_EFUSE_DATA_TEST_LSB 0xb9
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#define RT1308_EFUSE_STATUS_1 0xba
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#define RT1308_EFUSE_STATUS_2 0xbb
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#define RT1308_TCON_1 0xc0
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#define RT1308_TCON_2 0xc1
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#define RT1308_DUMMY_REG 0xf0
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#define RT1308_MAX_REG 0xff
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/* PLL1 M/N/K Code-1 (0x03) */
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#define RT1308_PLL1_K_SFT 24
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#define RT1308_PLL1_K_MASK (0x1f << 24)
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#define RT1308_PLL1_M_BYPASS_MASK (0x1 << 23)
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#define RT1308_PLL1_M_BYPASS_SFT 23
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#define RT1308_PLL1_M_BYPASS (0x1 << 23)
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#define RT1308_PLL1_M_MASK (0x3f << 16)
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#define RT1308_PLL1_M_SFT 16
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#define RT1308_PLL1_N_MASK (0x7f << 8)
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#define RT1308_PLL1_N_SFT 8
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/* CLOCK-1 (0x06) */
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#define RT1308_DIV_FS_SYS_MASK (0xf << 28)
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#define RT1308_DIV_FS_SYS_SFT 28
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#define RT1308_SEL_FS_SYS_MASK (0x7 << 24)
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#define RT1308_SEL_FS_SYS_SFT 24
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#define RT1308_SEL_FS_SYS_SRC_MCLK (0x0 << 24)
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#define RT1308_SEL_FS_SYS_SRC_BCLK (0x1 << 24)
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#define RT1308_SEL_FS_SYS_SRC_PLL (0x2 << 24)
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#define RT1308_SEL_FS_SYS_SRC_RCCLK (0x4 << 24)
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/* CLOCK-2 (0x08) */
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#define RT1308_DIV_PRE_PLL_MASK (0xf << 28)
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#define RT1308_DIV_PRE_PLL_SFT 28
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#define RT1308_SEL_PLL_SRC_MASK (0x7 << 24)
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#define RT1308_SEL_PLL_SRC_SFT 24
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#define RT1308_SEL_PLL_SRC_MCLK (0x0 << 24)
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#define RT1308_SEL_PLL_SRC_BCLK (0x1 << 24)
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#define RT1308_SEL_PLL_SRC_RCCLK (0x4 << 24)
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/* Clock Detect (0x0a) */
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#define RT1308_MCLK_DET_EN_MASK (0x1 << 25)
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#define RT1308_MCLK_DET_EN_SFT 25
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#define RT1308_MCLK_DET_EN (0x1 << 25)
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#define RT1308_BCLK_DET_EN_MASK (0x1 << 24)
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#define RT1308_BCLK_DET_EN_SFT 24
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#define RT1308_BCLK_DET_EN (0x1 << 24)
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/* DAC Setting (0x10) */
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#define RT1308_DVOL_MUTE_R_EN_SFT 7
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#define RT1308_DVOL_MUTE_L_EN_SFT 6
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/* I2S Setting-1 (0x15) */
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#define RT1308_I2S_DF_SEL_MASK (0x3 << 12)
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#define RT1308_I2S_DF_SEL_SFT 12
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#define RT1308_I2S_DF_SEL_I2S (0x0 << 12)
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#define RT1308_I2S_DF_SEL_LEFT (0x1 << 12)
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#define RT1308_I2S_DF_SEL_PCM_A (0x2 << 12)
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#define RT1308_I2S_DF_SEL_PCM_B (0x3 << 12)
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#define RT1308_I2S_DL_RX_SEL_MASK (0x7 << 4)
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#define RT1308_I2S_DL_RX_SEL_SFT 4
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#define RT1308_I2S_DL_RX_SEL_16B (0x0 << 4)
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#define RT1308_I2S_DL_RX_SEL_20B (0x1 << 4)
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#define RT1308_I2S_DL_RX_SEL_24B (0x2 << 4)
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#define RT1308_I2S_DL_RX_SEL_32B (0x3 << 4)
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#define RT1308_I2S_DL_RX_SEL_8B (0x4 << 4)
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#define RT1308_I2S_DL_TX_SEL_MASK (0x7 << 0)
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#define RT1308_I2S_DL_TX_SEL_SFT 0
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#define RT1308_I2S_DL_TX_SEL_16B (0x0 << 0)
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#define RT1308_I2S_DL_TX_SEL_20B (0x1 << 0)
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#define RT1308_I2S_DL_TX_SEL_24B (0x2 << 0)
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#define RT1308_I2S_DL_TX_SEL_32B (0x3 << 0)
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#define RT1308_I2S_DL_TX_SEL_8B (0x4 << 0)
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/* I2S Setting-2 (0x16) */
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#define RT1308_I2S_DL_SEL_MASK (0x7 << 24)
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#define RT1308_I2S_DL_SEL_SFT 24
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#define RT1308_I2S_DL_SEL_16B (0x0 << 24)
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#define RT1308_I2S_DL_SEL_20B (0x1 << 24)
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#define RT1308_I2S_DL_SEL_24B (0x2 << 24)
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#define RT1308_I2S_DL_SEL_32B (0x3 << 24)
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#define RT1308_I2S_DL_SEL_8B (0x4 << 24)
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#define RT1308_I2S_BCLK_MASK (0x1 << 14)
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#define RT1308_I2S_BCLK_SFT 14
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#define RT1308_I2S_BCLK_NORMAL (0x0 << 14)
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#define RT1308_I2S_BCLK_INV (0x1 << 14)
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/* Power Control-1 (0x32) */
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#define RT1308_POW_MBIAS20U (0x1 << 31)
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#define RT1308_POW_MBIAS20U_BIT 31
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#define RT1308_POW_ALDO (0x1 << 30)
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#define RT1308_POW_ALDO_BIT 30
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#define RT1308_POW_DBG (0x1 << 29)
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#define RT1308_POW_DBG_BIT 29
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#define RT1308_POW_DACL (0x1 << 28)
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#define RT1308_POW_DACL_BIT 28
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#define RT1308_POW_DAC1 (0x1 << 27)
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#define RT1308_POW_DAC1_BIT 27
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#define RT1308_POW_CLK25M (0x1 << 26)
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#define RT1308_POW_CLK25M_BIT 26
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#define RT1308_POW_ADC_R (0x1 << 25)
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#define RT1308_POW_ADC_R_BIT 25
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#define RT1308_POW_ADC_L (0x1 << 24)
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#define RT1308_POW_ADC_L_BIT 24
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#define RT1308_POW_DLDO (0x1 << 21)
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#define RT1308_POW_DLDO_BIT 21
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#define RT1308_POW_VREF (0x1 << 20)
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#define RT1308_POW_VREF_BIT 20
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#define RT1308_POW_MIXER_R (0x1 << 18)
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#define RT1308_POW_MIXER_R_BIT 18
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#define RT1308_POW_MIXER_L (0x1 << 17)
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#define RT1308_POW_MIXER_L_BIT 17
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#define RT1308_POW_MBIAS4U (0x1 << 16)
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#define RT1308_POW_MBIAS4U_BIT 16
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#define RT1308_POW_PLL2_LDO_EN (0x1 << 12)
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#define RT1308_POW_PLL2_LDO_EN_BIT 12
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#define RT1308_POW_PLL2B_EN (0x1 << 11)
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#define RT1308_POW_PLL2B_EN_BIT 11
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#define RT1308_POW_PLL2F_EN (0x1 << 10)
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#define RT1308_POW_PLL2F_EN_BIT 10
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#define RT1308_POW_PLL2F2_EN (0x1 << 9)
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#define RT1308_POW_PLL2F2_EN_BIT 9
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#define RT1308_POW_PLL2B2_EN (0x1 << 8)
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#define RT1308_POW_PLL2B2_EN_BIT 8
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/* Power Control-2 (0x36) */
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#define RT1308_POW_PDB_SRC_BIT (0x1 << 27)
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#define RT1308_POW_PDB_MN_BIT (0x1 << 25)
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#define RT1308_POW_PDB_REG_BIT (0x1 << 24)
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/* System Clock Source */
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enum {
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RT1308_FS_SYS_S_MCLK,
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RT1308_FS_SYS_S_BCLK,
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RT1308_FS_SYS_S_PLL,
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RT1308_FS_SYS_S_RCCLK, /* 25.0 MHz */
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};
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/* PLL Source */
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enum {
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RT1308_PLL_S_MCLK,
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RT1308_PLL_S_BCLK,
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RT1308_PLL_S_RCCLK,
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};
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enum {
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RT1308_AIF1,
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RT1308_AIFS
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};
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#endif /* end of _RT1308_H_ */
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