Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-25 05:32:00 +00:00
Code Issues Packages Projects Releases Wiki Activity
088c588fff
linux/drivers/cache/sifive_ccache.c

351 lines
9.1 KiB
C
Raw Normal View History

soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* SiFive composable cache controller Driver
*
* Copyright (C) 2018-2022 SiFive, Inc.
*
*/
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:15 +00:00
#define pr_fmt(fmt) "CCACHE: " fmt
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
#include <linux/align.h>
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
#include <linux/debugfs.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/device.h>
soc: sifive: ccache: define the macro for the register shifts Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:16 +00:00
#include <linux/bitfield.h>
cache: sifive_ccache: Partially convert to a platform driver Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") broke ccache initialization because the PLIC IRQ domain is no longer available during an arch_initcall: [ 0.087229] irq: no irq domain found for interrupt-controller@c000000 ! [ 0.087255] CCACHE: Could not request IRQ 0 Fix this by moving the IRQ handling code to a platform driver. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-27 05:45:24 +00:00
#include <linux/platform_device.h>
#include <linux/property.h>
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
#include <asm/cacheflush.h>
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
#include <asm/cacheinfo.h>
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
#include <asm/dma-noncoherent.h>
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
#include <soc/sifive/sifive_ccache.h>
#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120
#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124
#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128
#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
#define SIFIVE_CCACHE_CONFIG 0x00
soc: sifive: ccache: define the macro for the register shifts Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:16 +00:00
#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
#define SIFIVE_CCACHE_FLUSH64 0x200
#define SIFIVE_CCACHE_FLUSH32 0x240
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
#define SIFIVE_CCACHE_WAYENABLE 0x08
#define SIFIVE_CCACHE_ECCINJECTERR 0x40
#define SIFIVE_CCACHE_MAX_ECCINTR 4
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
#define SIFIVE_CCACHE_LINE_SIZE 64
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
static void __iomem *ccache_base;
static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
static struct riscv_cacheinfo_ops ccache_cache_ops;
soc: sifive: ccache: determine the cache level from dts Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:13 +00:00
static int level;
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
enum {
DIR_CORR = 0,
DATA_CORR,
DATA_UNCORR,
DIR_UNCORR,
};
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
enum {
QUIRK_NONSTANDARD_CACHE_OPS = BIT(0),
QUIRK_BROKEN_DATA_UNCORR = BIT(1),
};
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
#ifdef CONFIG_DEBUG_FS
static struct dentry *sifive_test;
static ssize_t ccache_write(struct file *file, const char __user *data,
size_t count, loff_t *ppos)
{
unsigned int val;
if (kstrtouint_from_user(data, count, 0, &val))
return -EINVAL;
if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
else
return -EINVAL;
return count;
}
static const struct file_operations ccache_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.write = ccache_write
};
static void setup_sifive_debug(void)
{
sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
debugfs_create_file("sifive_debug_inject_error", 0200,
sifive_test, NULL, &ccache_fops);
}
#endif
static void ccache_config_read(void)
{
soc: sifive: ccache: reduce printing on init The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:14 +00:00
u32 cfg;
cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
soc: sifive: ccache: define the macro for the register shifts Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:16 +00:00
pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
soc: sifive: ccache: reduce printing on init The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:14 +00:00
cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:15 +00:00
pr_info("Index of the largest way enabled: %u\n", cfg);
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
}
static const struct of_device_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
{ .compatible = "starfive,jh7100-ccache",
.data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
{ .compatible = "sifive,ccache0" },
{ /* end of table */ }
};
static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
int register_sifive_ccache_error_notifier(struct notifier_block *nb)
{
return atomic_notifier_chain_register(&ccache_err_chain, nb);
}
EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
{
return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
}
EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
static void ccache_flush_range(phys_addr_t start, size_t len)
{
phys_addr_t end = start + len;
phys_addr_t line;
if (!len)
return;
mb();
for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
line += SIFIVE_CCACHE_LINE_SIZE) {
#ifdef CONFIG_32BIT
writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
#else
writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
#endif
mb();
}
}
static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {
.wback = &ccache_flush_range,
.inv = &ccache_flush_range,
.wback_inv = &ccache_flush_range,
};
#endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
static int ccache_largest_wayenabled(void)
{
return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
}
static ssize_t number_of_ways_enabled_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%u\n", ccache_largest_wayenabled());
}
static DEVICE_ATTR_RO(number_of_ways_enabled);
static struct attribute *priv_attrs[] = {
&dev_attr_number_of_ways_enabled.attr,
NULL,
};
static const struct attribute_group priv_attr_group = {
.attrs = priv_attrs,
};
static const struct attribute_group *ccache_get_priv_group(struct cacheinfo
*this_leaf)
{
/* We want to use private group for composable cache only */
soc: sifive: ccache: determine the cache level from dts Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:13 +00:00
if (this_leaf->level == level)
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
return &priv_attr_group;
else
return NULL;
}
static irqreturn_t ccache_int_handler(int irq, void *device)
{
unsigned int add_h, add_l;
if (irq == g_irq[DIR_CORR]) {
add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:15 +00:00
pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l);
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
/* Reading this register clears the DirError interrupt sig */
readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
atomic_notifier_call_chain(&ccache_err_chain,
SIFIVE_CCACHE_ERR_TYPE_CE,
"DirECCFix");
}
if (irq == g_irq[DIR_UNCORR]) {
add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH);
add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW);
/* Reading this register clears the DirFail interrupt sig */
readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT);
atomic_notifier_call_chain(&ccache_err_chain,
SIFIVE_CCACHE_ERR_TYPE_UE,
"DirECCFail");
panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
}
if (irq == g_irq[DATA_CORR]) {
add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:15 +00:00
pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l);
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
/* Reading this register clears the DataError interrupt sig */
readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
atomic_notifier_call_chain(&ccache_err_chain,
SIFIVE_CCACHE_ERR_TYPE_CE,
"DatECCFix");
}
if (irq == g_irq[DATA_UNCORR]) {
add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:15 +00:00
pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l);
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
/* Reading this register clears the DataFail interrupt sig */
readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
atomic_notifier_call_chain(&ccache_err_chain,
SIFIVE_CCACHE_ERR_TYPE_UE,
"DatECCFail");
}
return IRQ_HANDLED;
}
cache: sifive_ccache: Partially convert to a platform driver Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") broke ccache initialization because the PLIC IRQ domain is no longer available during an arch_initcall: [ 0.087229] irq: no irq domain found for interrupt-controller@c000000 ! [ 0.087255] CCACHE: Could not request IRQ 0 Fix this by moving the IRQ handling code to a platform driver. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-27 05:45:24 +00:00
static int sifive_ccache_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
unsigned long quirks;
int intr_num, rc;
quirks = (unsigned long)device_get_match_data(dev);
intr_num = platform_irq_count(pdev);
if (!intr_num)
return dev_err_probe(dev, -ENODEV, "No interrupts property\n");
for (int i = 0; i < intr_num; i++) {
if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
continue;
g_irq[i] = platform_get_irq(pdev, i);
if (g_irq[i] < 0)
return g_irq[i];
rc = devm_request_irq(dev, g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
if (rc)
return dev_err_probe(dev, rc, "Could not request IRQ %d\n", g_irq[i]);
}
return 0;
}
static struct platform_driver sifive_ccache_driver = {
.probe = sifive_ccache_probe,
.driver = {
.name = "sifive_ccache",
.of_match_table = sifive_ccache_ids,
},
};
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
static int __init sifive_ccache_init(void)
{
struct device_node *np;
struct resource res;
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
const struct of_device_id *match;
cache: sifive_ccache: Silence unused variable warning With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns: drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init': drivers/cache/sifive_ccache.c:293:23: warning: variable 'quirks' set but not used [-Wunused-but-set-variable] 293 | unsigned long quirks; | ^~~~~~ This is expected, since QUIRK_NONSTANDARD_CACHE_OPS is the only quirk still handled in this function. Fixes: c90847bcbfb6 ("cache: sifive_ccache: Partially convert to a platform driver") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202403311253.Z4NvIBxI-lkp@intel.com/ Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-04-10 23:22:03 +00:00
unsigned long quirks __maybe_unused;
cache: sifive_ccache: Partially convert to a platform driver Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") broke ccache initialization because the PLIC IRQ domain is no longer available during an arch_initcall: [ 0.087229] irq: no irq domain found for interrupt-controller@c000000 ! [ 0.087255] CCACHE: Could not request IRQ 0 Fix this by moving the IRQ handling code to a platform driver. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-27 05:45:24 +00:00
int rc;
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
if (!np)
return -ENODEV;
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
quirks = (uintptr_t)match->data;
soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init() The device_node pointer returned by of_find_matching_node() with refcount incremented, when finish using it, the refcount need be decreased. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-18 02:31:49 +00:00
if (of_address_to_resource(np, 0, &res)) {
rc = -ENODEV;
goto err_node_put;
}
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
ccache_base = ioremap(res.start, resource_size(&res));
soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init() The device_node pointer returned by of_find_matching_node() with refcount incremented, when finish using it, the refcount need be decreased. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-18 02:31:49 +00:00
if (!ccache_base) {
rc = -ENOMEM;
goto err_node_put;
}
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init() Add missing iounmap() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-18 02:31:47 +00:00
if (of_property_read_u32(np, "cache-level", &level)) {
rc = -ENOENT;
goto err_unmap;
}
soc: sifive: ccache: determine the cache level from dts Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:13 +00:00
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
riscv_noncoherent_supported();
riscv_noncoherent_register_cache_ops(&ccache_mgmt_ops);
}
#endif
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
ccache_config_read();
ccache_cache_ops.get_priv_group = ccache_get_priv_group;
riscv_set_cacheinfo_ops(&ccache_cache_ops);
#ifdef CONFIG_DEBUG_FS
setup_sifive_debug();
#endif
cache: sifive_ccache: Partially convert to a platform driver Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") broke ccache initialization because the PLIC IRQ domain is no longer available during an arch_initcall: [ 0.087229] irq: no irq domain found for interrupt-controller@c000000 ! [ 0.087255] CCACHE: Could not request IRQ 0 Fix this by moving the IRQ handling code to a platform driver. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-27 05:45:24 +00:00
rc = platform_driver_register(&sifive_ccache_driver);
if (rc)
goto err_unmap;
of_node_put(np);
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
return 0;
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init() Add missing iounmap() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-18 02:31:47 +00:00
err_unmap:
iounmap(ccache_base);
soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init() The device_node pointer returned by of_find_matching_node() with refcount incremented, when finish using it, the refcount need be decreased. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-18 02:31:49 +00:00
err_node_put:
of_node_put(np);
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init() Add missing iounmap() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-18 02:31:47 +00:00
return rc;
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-13 06:18:12 +00:00
}
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-31 14:14:44 +00:00
arch_initcall(sifive_ccache_init);
Reference in New Issue Copy Permalink