2019-06-01 08:08:55 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2008-05-23 08:32:46 +00:00
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/*
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* Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Tony Li <tony.li@freescale.com>
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* Jason Jin <Jason.jin@freescale.com>
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*/
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#ifndef _POWERPC_SYSDEV_FSL_MSI_H
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#define _POWERPC_SYSDEV_FSL_MSI_H
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powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
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#include <linux/of.h>
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2008-08-05 23:10:02 +00:00
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#include <asm/msi_bitmap.h>
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2013-06-21 10:59:14 +00:00
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#define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */
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#define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */
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#define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1
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2008-05-23 08:32:46 +00:00
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#define IRQS_PER_MSI_REG 32
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2013-06-21 10:59:14 +00:00
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#define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
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2008-05-23 08:32:46 +00:00
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2011-12-13 20:51:59 +00:00
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#define FSL_PIC_IP_MASK 0x0000000F
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#define FSL_PIC_IP_MPIC 0x00000001
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#define FSL_PIC_IP_IPIC 0x00000002
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#define FSL_PIC_IP_VMPIC 0x00000003
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2008-05-23 08:32:46 +00:00
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2015-02-26 07:23:08 +00:00
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#define MSI_HW_ERRATA_ENDIAN 0x00000010
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2014-08-19 11:25:01 +00:00
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struct fsl_msi_cascade_data;
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2008-05-23 08:32:46 +00:00
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struct fsl_msi {
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2012-02-14 21:06:50 +00:00
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struct irq_domain *irqhost;
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2008-05-23 08:32:46 +00:00
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unsigned long cascade_irq;
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2011-09-23 17:41:35 +00:00
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u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
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2013-06-21 10:59:14 +00:00
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u32 ibs_shift; /* Shift of interrupt bit select */
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u32 srs_shift; /* Shift of the shared interrupt register select */
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2008-05-23 08:32:46 +00:00
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void __iomem *msi_regs;
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u32 feature;
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2014-08-19 11:25:01 +00:00
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struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
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2008-05-23 08:32:46 +00:00
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2008-08-05 23:10:02 +00:00
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struct msi_bitmap bitmap;
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2010-04-22 08:31:36 +00:00
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struct list_head list; /* support multiple MSI banks */
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powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
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phandle phandle;
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2008-05-23 08:32:46 +00:00
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};
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#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
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