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572 lines
15 KiB
ArmAsm
572 lines
15 KiB
ArmAsm
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/*
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* Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARC
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Nov 2010:
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* -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
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* -To maintain the slot size of 8 bytes/vector, added nop, which is
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* not executed at runtime.
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*
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* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
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* -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
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* -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
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* need ptregs anymore
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*
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* Vineetg: Oct 2009
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* -In a rare scenario, Process gets a Priv-V exception and gets scheduled
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* out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
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* active (AE bit enabled). This causes a double fault for a subseq valid
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* exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
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* Instr Error could also cause similar scenario, so same there as well.
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*
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* Vineetg: Aug 28th 2008: Bug #94984
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* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
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* Normally CPU does this automatically, however when doing FAKE rtie,
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* we need to explicitly do this. The problem in macros
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* FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
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* was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
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* setting it and not clearing it clears ZOL context
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*
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* Vineetg: Dec 22, 2007
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* Minor Surgery of Low Level ISR to make it SMP safe
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* - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
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* - _current_task is made an array of NR_CPUS
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* - Access of _current_task wrapped inside a macro so that if hardware
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* team agrees for a dedicated reg, no other code is touched
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*
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* Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
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*/
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/*------------------------------------------------------------------
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* Function ABI
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*------------------------------------------------------------------
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*
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* Arguments r0 - r7
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* Caller Saved Registers r0 - r12
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* Callee Saved Registers r13- r25
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* Global Pointer (gp) r26
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* Frame Pointer (fp) r27
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* Stack Pointer (sp) r28
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* Interrupt link register (ilink1) r29
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* Interrupt link register (ilink2) r30
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* Branch link register (blink) r31
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*------------------------------------------------------------------
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*/
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.cpu A7
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;############################ Vector Table #################################
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.macro VECTOR lbl
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#if 1 /* Just in case, build breaks */
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j \lbl
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#else
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b \lbl
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nop
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#endif
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.endm
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.section .vector, "ax",@progbits
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.align 4
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/* Each entry in the vector table must occupy 2 words. Since it is a jump
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* across sections (.vector to .text) we are gauranteed that 'j somewhere'
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* will use the 'j limm' form of the intrsuction as long as somewhere is in
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* a section other than .vector.
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*/
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; ********* Critical System Events **********************
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VECTOR res_service ; 0x0, Restart Vector (0x0)
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VECTOR mem_service ; 0x8, Mem exception (0x1)
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VECTOR instr_service ; 0x10, Instrn Error (0x2)
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; ******************** Device ISRs **********************
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VECTOR handle_interrupt_level1
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VECTOR handle_interrupt_level1
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VECTOR handle_interrupt_level1
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VECTOR handle_interrupt_level1
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.rept 25
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VECTOR handle_interrupt_level1 ; Other devices
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.endr
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/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
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; ******************** Exceptions **********************
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VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
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VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
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VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
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VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
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; or Misaligned Access
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VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
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VECTOR EV_Trap ; 0x128, Trap exception (0x25)
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VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
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.rept 24
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VECTOR reserved ; Reserved Exceptions
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.endr
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#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
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#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
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#include <asm/errno.h>
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#include <asm/arcregs.h>
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#include <asm/irqflags.h>
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;##################### Scratch Mem for IRQ stack switching #############
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.section .data ; NOT .global
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.align 32
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.type int1_saved_reg, @object
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.size int1_saved_reg, 4
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int1_saved_reg:
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.zero 4
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; ---------------------------------------------
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.section .text, "ax",@progbits
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res_service: ; processor restart
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flag 0x1 ; not implemented
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nop
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nop
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reserved: ; processor restart
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rtie ; jump to processor initializations
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;##################### Interrupt Handling ##############################
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; ---------------------------------------------
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; Level 1 ISR
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; ---------------------------------------------
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ARC_ENTRY handle_interrupt_level1
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/* free up r9 as scratchpad */
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st r9, [@int1_saved_reg]
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;Which mode (user/kernel) was the system in when intr occured
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lr r9, [status32_l1]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_INT1
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lr r0, [icause1]
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and r0, r0, 0x1f
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bl.d @arch_do_IRQ
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mov r1, sp
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mov r8,0x1
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sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
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b ret_from_exception
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ARC_EXIT handle_interrupt_level1
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;################### Non TLB Exception Handling #############################
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; ---------------------------------------------
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; Instruction Error Exception Handler
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; ---------------------------------------------
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ARC_ENTRY instr_service
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EXCPN_PROLOG_FREEUP_REG r9
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_SYS
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lr r0, [ecr]
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lr r1, [efa]
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mov r2, sp
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FAKE_RET_FROM_EXCPN r9
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bl do_insterror_or_kprobe
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b ret_from_exception
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ARC_EXIT instr_service
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; ---------------------------------------------
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; Memory Error Exception Handler
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; ---------------------------------------------
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ARC_ENTRY mem_service
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EXCPN_PROLOG_FREEUP_REG r9
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_SYS
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lr r0, [ecr]
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lr r1, [efa]
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mov r2, sp
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bl do_memory_error
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b ret_from_exception
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ARC_EXIT mem_service
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; ---------------------------------------------
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; Machine Check Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_MachineCheck
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EXCPN_PROLOG_FREEUP_REG r9
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_SYS
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lr r0, [ecr]
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lr r1, [efa]
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mov r2, sp
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brne r0, 0x200100, 1f
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bl do_tlb_overlap_fault
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b ret_from_exception
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1:
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; DEAD END: can't do much, display Regs and HALT
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SAVE_CALLEE_SAVED_USER
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GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
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st sp, [r10, THREAD_CALLEE_REG]
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j do_machine_check_fault
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ARC_EXIT EV_MachineCheck
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; ---------------------------------------------
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; Protection Violation Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_TLBProtV
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EXCPN_PROLOG_FREEUP_REG r9
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;Which mode (user/kernel) was the system in when Exception occured
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_SYS
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;---------(3) Save some more regs-----------------
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; vineetg: Mar 6th: Random Seg Fault issue #1
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; ecr and efa were not saved in case an Intr sneaks in
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; after fake rtie
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;
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lr r3, [ecr]
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lr r4, [efa]
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; --------(4) Return from CPU Exception Mode ---------
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; Fake a rtie, but rtie to next label
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; That way, subsequently, do_page_fault ( ) executes in pure kernel
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; mode with further Exceptions enabled
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FAKE_RET_FROM_EXCPN r9
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;------ (5) Type of Protection Violation? ----------
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;
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; ProtV Hardware Exception is triggered for Access Faults of 2 types
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; -Access Violaton (WRITE to READ ONLY Page) - for linux COW
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; -Unaligned Access (READ/WRITE on odd boundary)
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;
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cmp r3, 0x230400 ; Misaligned data access ?
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beq 4f
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;========= (6a) Access Violation Processing ========
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cmp r3, 0x230100
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mov r1, 0x0 ; if LD exception ? write = 0
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mov.ne r1, 0x1 ; else write = 1
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mov r2, r4 ; faulting address
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mov r0, sp ; pt_regs
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bl do_page_fault
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b ret_from_exception
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;========== (6b) Non aligned access ============
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4:
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mov r0, r3 ; cause code
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mov r1, r4 ; faulting address
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mov r2, sp ; pt_regs
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bl do_misaligned_access
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b ret_from_exception
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ARC_EXIT EV_TLBProtV
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; ---------------------------------------------
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; Privilege Violation Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_PrivilegeV
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EXCPN_PROLOG_FREEUP_REG r9
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_SYS
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lr r0, [ecr]
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lr r1, [efa]
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mov r2, sp
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FAKE_RET_FROM_EXCPN r9
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bl do_privilege_fault
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b ret_from_exception
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ARC_EXIT EV_PrivilegeV
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; ---------------------------------------------
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; Extension Instruction Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_Extension
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EXCPN_PROLOG_FREEUP_REG r9
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_SYS
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lr r0, [ecr]
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lr r1, [efa]
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mov r2, sp
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bl do_extension_fault
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b ret_from_exception
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ARC_EXIT EV_Extension
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;################### Break Point TRAP ##########################
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; ======= (5b) Trap is due to Break-Point =========
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trap_with_param:
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;make sure orig_r8 is a positive value
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st NR_syscalls + 2, [sp, PT_orig_r8]
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mov r0, r12
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lr r1, [efa]
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mov r2, sp
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; Now that we have read EFA, its safe to do "fake" rtie
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; and get out of CPU exception mode
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FAKE_RET_FROM_EXCPN r11
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; Save callee regs in case gdb wants to have a look
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; SP will grow up by size of CALLEE Reg-File
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; NOTE: clobbers r12
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SAVE_CALLEE_SAVED_USER
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; save location of saved Callee Regs @ thread_struct->pc
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GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
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st sp, [r10, THREAD_CALLEE_REG]
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; Call the trap handler
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bl do_non_swi_trap
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; unwind stack to discard Callee saved Regs
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DISCARD_CALLEE_SAVED_USER
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b ret_from_exception
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;##################### Trap Handling ##############################
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;
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; EV_Trap caused by TRAP_S and TRAP0 instructions.
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;------------------------------------------------------------------
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; (1) System Calls
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; :parameters in r0-r7.
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; :r8 has the system call number
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; (2) Break Points
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;------------------------------------------------------------------
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ARC_ENTRY EV_Trap
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; Need at least 1 reg to code the early exception prolog
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EXCPN_PROLOG_FREEUP_REG r9
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;Which mode (user/kernel) was the system in when intr occured
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lr r9, [erstatus]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_TRAP
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;------- (4) What caused the Trap --------------
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lr r12, [ecr]
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and.f 0, r12, ECR_PARAM_MASK
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bnz trap_with_param
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; ======= (5a) Trap is due to System Call ========
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; Before doing anything, return from CPU Exception Mode
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FAKE_RET_FROM_EXCPN r11
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;============ This is normal System Call case ==========
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; Sys-call num shd not exceed the total system calls avail
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cmp r8, NR_syscalls
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mov.hi r0, -ENOSYS
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bhi ret_from_system_call
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; Offset into the syscall_table and call handler
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ld.as r9,[sys_call_table, r8]
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jl [r9] ; Entry into Sys Call Handler
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; fall through to ret_from_system_call
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ARC_EXIT EV_Trap
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ARC_ENTRY ret_from_system_call
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st r0, [sp, PT_r0] ; sys call return value in pt_regs
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; fall through yet again to ret_from_exception
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;############# Return from Intr/Excp/Trap (Linux Specifics) ##############
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;
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; If ret to user mode do we need to handle signals, schedule() et al.
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ARC_ENTRY ret_from_exception
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; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32
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ld r8, [sp, PT_status32] ; returning to User/Kernel Mode
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#ifdef CONFIG_PREEMPT
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bbit0 r8, STATUS_U_BIT, resume_kernel_mode
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#else
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bbit0 r8, STATUS_U_BIT, restore_regs
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#endif
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; Before returning to User mode check-for-and-complete any pending work
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; such as rescheduling/signal-delivery etc.
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resume_user_mode_begin:
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; Disable IRQs to ensures that chk for pending work itself is atomic
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; (and we don't end up missing a NEED_RESCHED/SIGPENDING due to an
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; interim IRQ).
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IRQ_DISABLE r10
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|
; Fast Path return to user mode if no pending work
|
||
|
GET_CURR_THR_INFO_FLAGS r9
|
||
|
and.f 0, r9, _TIF_WORK_MASK
|
||
|
bz restore_regs
|
||
|
|
||
|
; --- (Slow Path #1) task preemption ---
|
||
|
bbit0 r9, TIF_NEED_RESCHED, .Lchk_pend_signals
|
||
|
mov blink, resume_user_mode_begin ; tail-call to U mode ret chks
|
||
|
b @schedule ; BTST+Bnz causes relo error in link
|
||
|
|
||
|
.Lchk_pend_signals:
|
||
|
IRQ_ENABLE r10
|
||
|
|
||
|
; --- (Slow Path #2) pending signal ---
|
||
|
mov r0, sp ; pt_regs for arg to do_signal()/do_notify_resume()
|
||
|
|
||
|
bbit0 r9, TIF_SIGPENDING, .Lchk_notify_resume
|
||
|
|
||
|
; save CALLEE Regs.
|
||
|
; (i) If this signal causes coredump - full regfile needed
|
||
|
; (ii) If signal is SIGTRAP/SIGSTOP, task is being traced thus
|
||
|
; tracer might call PEEKUSR(CALLEE reg)
|
||
|
;
|
||
|
; NOTE: SP will grow up by size of CALLEE Reg-File
|
||
|
SAVE_CALLEE_SAVED_USER ; clobbers r12
|
||
|
|
||
|
; save location of saved Callee Regs @ thread_struct->callee
|
||
|
GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
|
||
|
st sp, [r10, THREAD_CALLEE_REG]
|
||
|
|
||
|
bl @do_signal
|
||
|
|
||
|
; unwind SP for cheap discard of Callee saved Regs
|
||
|
DISCARD_CALLEE_SAVED_USER
|
||
|
|
||
|
b resume_user_mode_begin ; loop back to start of U mode ret
|
||
|
|
||
|
; --- (Slow Path #3) notify_resume ---
|
||
|
.Lchk_notify_resume:
|
||
|
btst r9, TIF_NOTIFY_RESUME
|
||
|
blnz @do_notify_resume
|
||
|
b resume_user_mode_begin ; unconditionally back to U mode ret chks
|
||
|
; for single exit point from this block
|
||
|
|
||
|
#ifdef CONFIG_PREEMPT
|
||
|
|
||
|
resume_kernel_mode:
|
||
|
|
||
|
; Can't preempt if preemption disabled
|
||
|
GET_CURR_THR_INFO_FROM_SP r10
|
||
|
ld r8, [r10, THREAD_INFO_PREEMPT_COUNT]
|
||
|
brne r8, 0, restore_regs
|
||
|
|
||
|
; check if this task's NEED_RESCHED flag set
|
||
|
ld r9, [r10, THREAD_INFO_FLAGS]
|
||
|
bbit0 r9, TIF_NEED_RESCHED, restore_regs
|
||
|
|
||
|
IRQ_DISABLE r9
|
||
|
|
||
|
; Invoke PREEMPTION
|
||
|
bl preempt_schedule_irq
|
||
|
|
||
|
; preempt_schedule_irq() always returns with IRQ disabled
|
||
|
#endif
|
||
|
|
||
|
; fall through
|
||
|
|
||
|
;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
|
||
|
;
|
||
|
; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
|
||
|
; IRQ shd definitely not happen between now and rtie
|
||
|
|
||
|
restore_regs :
|
||
|
|
||
|
; Disable Interrupts while restoring reg-file back
|
||
|
; XXX can this be optimised out
|
||
|
IRQ_DISABLE_SAVE r9, r10 ;@r10 has prisitine (pre-disable) copy
|
||
|
|
||
|
; Restore REG File. In case multiple Events outstanding,
|
||
|
; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
|
||
|
; Note that we use realtime STATUS32 (not pt_regs->status32) to
|
||
|
; decide that.
|
||
|
|
||
|
; if Returning from Exception
|
||
|
bbit0 r10, STATUS_AE_BIT, not_exception
|
||
|
RESTORE_ALL_SYS
|
||
|
rtie
|
||
|
|
||
|
; Not Exception so maybe Interrupts (Level 1 or 2)
|
||
|
|
||
|
not_exception:
|
||
|
|
||
|
bbit0 r10, STATUS_A1_BIT, not_level1_interrupt
|
||
|
|
||
|
;return from level 1
|
||
|
|
||
|
RESTORE_ALL_INT1
|
||
|
debug_marker_l1:
|
||
|
rtie
|
||
|
|
||
|
not_level1_interrupt:
|
||
|
|
||
|
;this case is for syscalls or Exceptions (with fake rtie)
|
||
|
|
||
|
RESTORE_ALL_SYS
|
||
|
debug_marker_syscall:
|
||
|
rtie
|
||
|
|
||
|
ARC_EXIT ret_from_exception
|
||
|
|
||
|
ARC_ENTRY ret_from_fork
|
||
|
; when the forked child comes here from the __switch_to function
|
||
|
; r0 has the last task pointer.
|
||
|
; put last task in scheduler queue
|
||
|
bl @schedule_tail
|
||
|
b @ret_from_exception
|
||
|
ARC_EXIT ret_from_fork
|