2015-04-09 19:20:41 +00:00
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/*
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* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2015, Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/qcom_scm.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#define MAX_PMIC_DATA 2
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#define MAX_SEQ_DATA 64
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#define SPM_CTL_INDEX 0x7f
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#define SPM_CTL_INDEX_SHIFT 4
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#define SPM_CTL_EN BIT(0)
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enum pm_sleep_mode {
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PM_SLEEP_MODE_STBY,
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PM_SLEEP_MODE_RET,
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PM_SLEEP_MODE_SPC,
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PM_SLEEP_MODE_PC,
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PM_SLEEP_MODE_NR,
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};
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enum spm_reg {
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SPM_REG_CFG,
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SPM_REG_SPM_CTL,
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SPM_REG_DLY,
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SPM_REG_PMIC_DLY,
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SPM_REG_PMIC_DATA_0,
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SPM_REG_PMIC_DATA_1,
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SPM_REG_VCTL,
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SPM_REG_SEQ_ENTRY,
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SPM_REG_SPM_STS,
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SPM_REG_PMIC_STS,
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SPM_REG_NR,
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};
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struct spm_reg_data {
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const u8 *reg_offset;
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u32 spm_cfg;
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u32 spm_dly;
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u32 pmic_dly;
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u32 pmic_data[MAX_PMIC_DATA];
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u8 seq[MAX_SEQ_DATA];
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u8 start_index[PM_SLEEP_MODE_NR];
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};
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struct spm_driver_data {
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void __iomem *reg_base;
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const struct spm_reg_data *reg_data;
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};
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static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8974, 8084 */
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static const struct spm_reg_data spm_reg_8974_8084_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
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0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
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0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x20,
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[SPM_REG_PMIC_DLY] = 0x24,
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[SPM_REG_PMIC_DATA_0] = 0x28,
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[SPM_REG_PMIC_DATA_1] = 0x2C,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8064 */
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static const struct spm_reg_data spm_reg_8064_cpu = {
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.reg_offset = spm_reg_offset_v1_1,
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.spm_cfg = 0x1F,
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.pmic_dly = 0x02020004,
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.pmic_data[0] = 0x0084009C,
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.pmic_data[1] = 0x00A4001C,
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.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
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0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
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typedef int (*idle_fn)(int);
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static DEFINE_PER_CPU(idle_fn*, qcom_idle_ops);
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static inline void spm_register_write(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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if (drv->reg_data->reg_offset[reg])
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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}
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/* Ensure a guaranteed write, before return */
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static inline void spm_register_write_sync(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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u32 ret;
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if (!drv->reg_data->reg_offset[reg])
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return;
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do {
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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ret = readl_relaxed(drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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if (ret == val)
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break;
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cpu_relax();
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} while (1);
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}
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static inline u32 spm_register_read(struct spm_driver_data *drv,
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enum spm_reg reg)
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{
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return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
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}
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static void spm_set_low_power_mode(struct spm_driver_data *drv,
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enum pm_sleep_mode mode)
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{
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u32 start_index;
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u32 ctl_val;
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start_index = drv->reg_data->start_index[mode];
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ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
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ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
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ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
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ctl_val |= SPM_CTL_EN;
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spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
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}
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static int qcom_pm_collapse(unsigned long int unused)
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{
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qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
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/*
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* Returns here only if there was a pending interrupt and we did not
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* power down as a result.
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*/
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return -1;
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}
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static int qcom_cpu_spc(int cpu)
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{
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int ret;
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struct spm_driver_data *drv = per_cpu(cpu_spm_drv, cpu);
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
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ret = cpu_suspend(0, qcom_pm_collapse);
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/*
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* ARM common code executes WFI without calling into our driver and
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* if the SPM mode is not reset, then we may accidently power down the
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* cpu when we intended only to gate the cpu clock.
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* Ensure the state is set to standby before returning.
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*/
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
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return ret;
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}
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static int qcom_idle_enter(int cpu, unsigned long index)
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{
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return per_cpu(qcom_idle_ops, cpu)[index](cpu);
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}
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static const struct of_device_id qcom_idle_state_match[] __initconst = {
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{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
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{ },
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};
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static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
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{
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const struct of_device_id *match_id;
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struct device_node *state_node;
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int i;
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int state_count = 1;
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idle_fn idle_fns[CPUIDLE_STATE_MAX];
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idle_fn *fns;
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cpumask_t mask;
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bool use_scm_power_down = false;
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for (i = 0; ; i++) {
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state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
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if (!state_node)
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break;
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if (!of_device_is_available(state_node))
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continue;
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if (i == CPUIDLE_STATE_MAX) {
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pr_warn("%s: cpuidle states reached max possible\n",
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__func__);
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break;
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}
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match_id = of_match_node(qcom_idle_state_match, state_node);
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if (!match_id)
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return -ENODEV;
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idle_fns[state_count] = match_id->data;
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/* Check if any of the states allow power down */
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if (match_id->data == qcom_cpu_spc)
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use_scm_power_down = true;
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state_count++;
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}
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if (state_count == 1)
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goto check_spm;
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fns = devm_kcalloc(get_cpu_device(cpu), state_count, sizeof(*fns),
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GFP_KERNEL);
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if (!fns)
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return -ENOMEM;
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for (i = 1; i < state_count; i++)
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fns[i] = idle_fns[i];
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if (use_scm_power_down) {
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/* We have atleast one power down mode */
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cpumask_clear(&mask);
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cpumask_set_cpu(cpu, &mask);
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2015-06-02 19:12:58 +00:00
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qcom_scm_set_warm_boot_addr(cpu_resume_arm, &mask);
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2015-04-09 19:20:41 +00:00
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}
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per_cpu(qcom_idle_ops, cpu) = fns;
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/*
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* SPM probe for the cpu should have happened by now, if the
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* SPM device does not exist, return -ENXIO to indicate that the
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* cpu does not support idle states.
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*/
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check_spm:
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return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENXIO;
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}
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static struct cpuidle_ops qcom_cpuidle_ops __initdata = {
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.suspend = qcom_idle_enter,
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.init = qcom_cpuidle_init,
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};
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CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v1, "qcom,kpss-acc-v1", &qcom_cpuidle_ops);
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CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v2, "qcom,kpss-acc-v2", &qcom_cpuidle_ops);
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static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
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int *spm_cpu)
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{
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struct spm_driver_data *drv = NULL;
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struct device_node *cpu_node, *saw_node;
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int cpu;
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2016-01-17 00:02:56 +00:00
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bool found = 0;
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2015-04-09 19:20:41 +00:00
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for_each_possible_cpu(cpu) {
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node)
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continue;
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saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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found = (saw_node == pdev->dev.of_node);
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of_node_put(saw_node);
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of_node_put(cpu_node);
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if (found)
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break;
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}
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if (found) {
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drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
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if (drv)
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*spm_cpu = cpu;
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}
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return drv;
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}
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static const struct of_device_id spm_match_table[] = {
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{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
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.data = &spm_reg_8064_cpu },
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{ },
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};
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static int spm_dev_probe(struct platform_device *pdev)
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{
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struct spm_driver_data *drv;
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struct resource *res;
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const struct of_device_id *match_id;
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void __iomem *addr;
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int cpu;
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drv = spm_get_drv(pdev, &cpu);
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if (!drv)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(drv->reg_base))
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return PTR_ERR(drv->reg_base);
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match_id = of_match_node(spm_match_table, pdev->dev.of_node);
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if (!match_id)
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return -ENODEV;
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drv->reg_data = match_id->data;
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/* Write the SPM sequences first.. */
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addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
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__iowrite32_copy(addr, drv->reg_data->seq,
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ARRAY_SIZE(drv->reg_data->seq) / 4);
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|
|
|
|
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/*
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|
|
|
* ..and then the control registers.
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|
|
|
* On some SoC if the control registers are written first and if the
|
|
|
|
* CPU was held in reset, the reset signal could trigger the SPM state
|
|
|
|
* machine, before the sequences are completely written.
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|
|
|
*/
|
|
|
|
spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
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|
|
|
spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
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|
|
|
spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
|
|
|
|
spm_register_write(drv, SPM_REG_PMIC_DATA_0,
|
|
|
|
drv->reg_data->pmic_data[0]);
|
|
|
|
spm_register_write(drv, SPM_REG_PMIC_DATA_1,
|
|
|
|
drv->reg_data->pmic_data[1]);
|
|
|
|
|
|
|
|
/* Set up Standby as the default low power mode */
|
|
|
|
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
|
|
|
|
|
|
|
|
per_cpu(cpu_spm_drv, cpu) = drv;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver spm_driver = {
|
|
|
|
.probe = spm_dev_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "saw",
|
|
|
|
.of_match_table = spm_match_table,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(spm_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("SAW power controller driver");
|
|
|
|
MODULE_ALIAS("platform:saw");
|