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u-boot/board/xilinx/zynq
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Michal Simek 2fe55d1827 xilinx: zynq: Enable early eeprom decoding 
Xilinx Zynq evaluation boards have factory program content in eeprom.
Enable reading and decoding eeprom content to get information about board
name, revision and especially getting ethernet mac address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/db334bd3c0a377074a43b7ae479fade98efb545f.1664265344.git.michal.simek@amd.com
2022-10-05 08:43:53 +02:00
..
zynq-cc108
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-dlc20-rev1.0
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-microzed
WS cleanup: remove excessive empty lines
2021-09-30 08:08:56 -04:00
zynq-zc702
WS cleanup: remove excessive empty lines
2021-09-30 08:08:56 -04:00
zynq-zc706
WS cleanup: remove excessive empty lines
2021-09-30 08:08:56 -04:00
zynq-zc770-xm010
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-zc770-xm011
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-zc770-xm011-x16
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-zc770-xm012
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-zc770-xm013
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-zed
WS cleanup: remove excessive empty lines
2021-09-30 08:08:56 -04:00
zynq-zturn
arm: zynq: Remove low level UART setting
2020-01-14 09:05:53 +01:00
zynq-zturn-v5
ARM: zynq: Add Z-turn board V5
2020-10-27 08:01:36 +01:00
zynq-zybo
WS cleanup: remove trailing empty lines
2021-09-30 08:08:56 -04:00
zynq-zybo-z7
arm: zynq: zybo z7: fix MIO init issue
2020-02-28 12:04:10 +01:00
.gitignore
…
board.c
xilinx: zynq: Enable early eeprom decoding
2022-10-05 08:43:53 +02:00
bootimg.c
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
cmds.c
global: Convert simple_strtoul() with hex to hextoul()
2021-08-02 13:32:14 -04:00
Kconfig
…
MAINTAINERS
Correct U-Boot upstream repository
2021-02-28 13:57:30 -05:00
Makefile
xilinx: common: Add Makefile to common folder
2020-10-27 08:13:32 +01:00
xil_io.h
…
zynq-cse-nand
…
zynq-cse-nor
…
zynq-cse-qspi-single
…