329d32a987
D1 contains a pin controller similar to previous SoCs, but with some register layout changes. It includes 6 interrupt-capable pin banks. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220713025233.27248-2-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>