Daniel Vetter 515ac2bb95
drm/i915: wire up gmbus irq handler ...
Only enables the interrupt and puts a irq handler into place, doesn't
do anything yet.
Unfortunately there's no gmbus interrupt support for gen2/3 (safe for
pnv, but there the irq is marked as "Test mode").
v2: Wire up the irq handler for vlv and gen4 properly.
v3: i915_enable_pipestat expects the mask bit, not the status bits ... and
for added hilarity those are rather inconsistently named.
Reviewed-by: Imre Deak <imre.deak@intel.com >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
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515ac2bb95