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47534 Commits

Author SHA1 Message Date
Harry Wentland
9f921b147b drm/amd/display: Debug-print reason for mode validation failure 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:27 -05:00
Harry Wentland
f2c7c55b0e drm/amd/display: Don't block dual-link DVI modes 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:27 -05:00
Harry Wentland
7e98ab1035 drm/amd/display: Don't allow dual-link DVI on all ASICs. 
Our APUs (Carrizo, Stoney, Raven) don't support it.

v2: Don't use is_apu as other ASICs might also not support it

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:26 -05:00
Harry Wentland
a39438f0b9 drm/amd/display: Debug print when validate_stream fails 
It might be good to understand why validate fails.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:26 -05:00
Yongqiang Sun
25292028d7 drm/amd/display: Disable eDP with a proper sequence. 
Proper sequence should be:
disable backlight
dp blank
disable output
edp power off

In enable accelatate mode, all the encoder and controller
are disabled, so move disable eDP to the function is the
easiest way to implement.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:25 -05:00
Tony Cheng
34d924f598 drm/amd/display: dal 3.1.28 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:25 -05:00
Harry Wentland
3d5bae9eb7 drm/amd/display: Pass signal directly to enable_tmds_output 
This makes the check for HDMI and dual-link DVI a bit more
straightforward.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:24 -05:00
Harry Wentland
64245fa72d drm/amd/display: Remove unnecessary fail labels in create_stream_for_sink 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:23 -05:00
Harry Wentland
eb6c24a3e6 drm/amd/display: Move MAX_TMDS_CLOCK define to header 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:23 -05:00
Yongqiang Sun
91178796ba drm/amd/display: disable eDP backlight for extend monitor only reboot use case. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:22 -05:00
Krunoslav Kovac
146a9f6368 drm/amd/display: Pass full 3x4 remap matrix for color transform 
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:22 -05:00
Mikita Lipski
03736f4cf8 drm/amd/display: Prevent master programming in multisync 
Verify that the stream is master - and program only the slave displays

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:21 -05:00
Roman Li
3bc4aaa952 drm/amd/display: Fix FBC topology change 
With FBC enabled there was a potential null-deref
on topology change due to hardcorded pipe index.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:21 -05:00
Yongqiang Sun
8d6a741bf6 drm/amd/display: Use pipe_control_lock instead of tg lock. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:20 -05:00
Jerry (Fangzhi) Zuo
7deff5454a drm/amd/display: Fix topology change issue in MST rehook 
When topology changed and rehook up MST display to the same DP
connector, need to take care of drm_dp_mst_port object.

Due to the topology is changed, drm_dp_mst_port and corresponding
i2c_algorithm object could be NULL in such situation.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:20 -05:00
Roman Li
63b024c869 drm/amd/display: cleanup after FBC init rework 
After reworking FBC init for dynamic mem alloc
old FBC init code in DC became redundant.
Removing it.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:19 -05:00
Roman Li
42e67c3b3c drm/amd/display: make FBC mem alloc dynamic 
- FBC init reworked to alloc memory based on display mode.
- Removed asic-dependencies from dm

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:18 -05:00
Ken Chalmers
6d5d346f04 drm/amd/display: Eliminate several Maximus-specific code paths 
This allows Maximus emulation to more closely mirror actual silicon
execution.

* Enable pool->base.display_clock creation on Maximus.
* Enable rest of dce110_apply_ctx_to_hw on Maximus.
* Remove apply_ctx_to_hw_fpga (no longer necessary with the full
  dce110_apply_ctx_to_hw enabled).
* Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock
  for Maximus (this was the only fix-up necessary after enabling
  dce110_apply_ctx_to_hw; everything else works unmodified on
  Maximus).

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:18 -05:00
Ken Chalmers
73535feb17 drm/amd/display: Fix Maximus pixel clock programming 
Maximus testing now defaults to a 700 MHz emulated dispclk

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:17 -05:00
Charlene Liu
a8c40b0b5a drm/amd/display: PME sw wa to support waking AZ D3 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:17 -05:00
Fengguang Wu
02d170e264 drm/amdgpu: fix semicolon.cocci warnings 
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:281:2-3: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Fixes: 620f774f46 ("drm/amdgpu: separate VMID and PASID handling")
CC: Christian König <christian.koenig@amd.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:16 -05:00
Rex Zhu
4efe9b4794 drm/amd/pp: Refine code shorten variable name 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:16 -05:00
Rex Zhu
9bd2bae13d drm/amd/pp: Add a helper to convert VID to voltage value 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:15 -05:00
Alex Deucher
64b9342f31 drm/amdgpu: drop extra tlb invalidation in gpuvm 
We only need to flush the HDP here, not invalidate the TLB.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:14 -05:00
Alex Deucher
b1d128689f drm/amdgpu: adjust HDP write queue flushing for tlb invalidation 
Separate tlb invalidation and hdp flushing and move the HDP
flush to the caller.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:14 -05:00
Alex Deucher
73c732405f drm/amdgpu: add HDP asic callbacks for SOC15 (v2) 
Needed to flush and invalidate the HDP block using the CPU.

v2: use preferred register on soc15.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com> (v1)
 2018-02-19 14:17:13 -05:00
Alex Deucher
dd8d07f2fb drm/amdgpu: add HDP asic callbacks for VI 
Needed to flush and invalidate the HDP block using the CPU.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
 2018-02-19 14:17:13 -05:00
Alex Deucher
13854c60d7 drm/amdgpu: add HDP asic callbacks for CIK 
Needed to flush and invalidate the HDP block using the CPU.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
 2018-02-19 14:17:12 -05:00
Alex Deucher
2d5e0807ed drm/amdgpu: add HDP asic callbacks for SI 
Needed to flush and invalidate the HDP block using the CPU.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
 2018-02-19 14:17:12 -05:00
Alex Deucher
2df1b8b6a1 drm/amdgpu: add new asic callbacks for HDP flush/invalidation 
Needed to properly flush the HDP cache with the CPU from rather
than the GPU.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
 2018-02-19 14:17:11 -05:00
Andres Rodriguez
f8e3e0ee8f drm/amdgpu: bump version for gfx9 high priority compute 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:10 -05:00
Andres Rodriguez
761c77c195 drm/amdgpu: add high priority compute support for gfx9 
We follow the same approach as gfx8. The only changes are register
access macros.

Tested on vega10. The execution latency results fall within the expected
ranges from the polaris10 data.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:10 -05:00
Evan Quan
10cd19c877 drm/amd/powerplay: use ffs/fls instead of implementing our own 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:09 -05:00
Evan Quan
31a47dcab8 drm/amd/powerplay: export the thermal ranges of Carrizo (V2) 
V2: reuse the SMUThermal structure defined in pp_thermal.h

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:09 -05:00
Evan Quan
4ba082572a drm/amd/powerplay: export the thermal ranges of VI asics (V2) 
V2: move the SMU7Thermal structure to newly created header file

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:08 -05:00
Evan Quan
0a91ee0775 drm/amd/powerplay: export vega10 specific thermal ranges (V2) 
V2: new header file to hold the common SMU7Thermal structure

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:08 -05:00
Alex Deucher
77f208d91b drm/amd/powerplay: export thermal range through temp sysfs 
Populate the hwmon temp range as part of thermal controller setup.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:07 -05:00
Evan Quan
80cfd1db67 drm/amd/powerplay: new hw manager interface for retrieving device specific thermal range 
Added a new callback for asic specific backends to specify the temperature ranges.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:07 -05:00
Evan Quan
1357f0c5ac drm/amd/powerplay: new cgs interface setting dpm thermal range 
This will be used by powerplay to update the dpm temp range structure
used to interface with hwmon.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:06 -05:00
Evan Quan
4ad9d4dd65 drm/amd/powerplay: correct PP_TemperatureRange member type since negative values are part of the valid range 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:05 -05:00
Evan Quan
39199b803b drm/amd/powerplay: removed hwmgr_handle_task unused parameter and given a better name for 
other parameter

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:05 -05:00
Evan Quan
8053e976cf drm/amd/powerplay: remove unused parameter of phm_start_thermal_controller (v2) 
Unused.

v2: squash in warning fix (Harry)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:04 -05:00
Dmitry Rozhkov
94af870a63 drm/radeon: use raw buffer printk specifier 
printk format strings accepting a single subsequent argument
are shorter thus easier to read.

Instead of having format strings accepting 3 different arguments
pointing to first 3 bytes of the same buffer rewrite the format
string to accept only one argument - the buffer - with "%3ph"
specifier.

Signed-off-by: Dmitry Rozhkov <dmitry.rozhkov@linux.intel.com>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:04 -05:00
Julia Lawall
1446413f21 drm/amd/powerplay: drop unneeded newline 
PP_ASSERT_WITH_CODE prints a newline at the end of the message string,
so the message string does not need to include a newline explicitly.
Done using Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:03 -05:00
Kai-Heng Feng
06998a756a drm/edid: Add 6 bpc quirk for CPT panel in Asus UX303LA 
Similar to commit e10aec652f ("drm/edid: Add 6 bpc quirk for display
AEO model 0."), the EDID reports "DFP 1.x compliant TMDS" but it support
6bpc instead of 8 bpc.

Hence, use 6 bpc quirk for this panel.

Fixes: 196f954e25 ("drm/i915/dp: Revert "drm/i915/dp: fall back to 18 bpp when sink capability is unknown"")
BugLink: https://bugs.launchpad.net/bugs/1749420
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: <stable@vger.kernel.org> # v4.8+
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20180218085359.7817-1-kai.heng.feng@canonical.com
 2018-02-19 16:43:50 +01:00
Chris Wilson
2e4a5b2588 drm/i915: Prune gen8_gt_irq_handler 
The compiler is not automatically caching the i915->regs address inside
a register and emitting a load for every mmio access. For simple
functions like gen8_gt_irq_handler that are already using the raw
accessors, we can open-code them for substantial savings:

add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-83 (-83)
Function                                     old     new   delta
gen8_gt_irq_handler                          290     266     -24
gen8_gt_irq_ack                              181     122     -59
Total: Before=954637, After=954554, chg -0.01%

v2: Add raw_reg_read/raw_reg_write.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180219100926.16554-1-chris@chris-wilson.co.uk
 2018-02-19 15:38:59 +00:00
Chris Wilson
f0fd96f546 drm/i915: Track GT interrupt handling using the master iir 
Keep the master iir and use it to reduce the number of reads and writes
to the GT iir array, i.e. only the bits marked as set by the master iir
are valid inside GT iir array and will be handled during the interrupt.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180215073713.26985-1-chris@chris-wilson.co.uk
 2018-02-19 15:38:58 +00:00
Chris Wilson
acb79148dc drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use 
As the driver is called to handle circumstances beyond it's control, we
cannot assume that the pm_runtime core is happy to see us. For example,
if we are called from shrink_slab to free up our pages during suspend,
rpm may be disabled and pm_runtime_if_in_use() decides to fail with
-EINVAL rather than simply say no. This is expected to happen, so don't
warn.  For example,

[  217.429228] Suspending console(s) (use no_console_suspend to debug)
[  217.557179] sd 0:0:0:0: [sda] Synchronizing SCSI cache
[  217.559399] sd 0:0:0:0: [sda] Stopping disk
[  218.661567] i915 0000:00:02.0: Resetting chip after gpu hang
[  219.523879] ------------[ cut here ]------------
[  219.524474] pm_runtime_get_if_in_use() failed: -22
[  219.524817] WARNING: CPU: 1 PID: 14 at drivers/gpu/drm/i915/intel_runtime_pm.c:3351 intel_runtime_pm_get_if_in_use+0xe3/0x150 [i915]
[  219.524836] Modules linked in: vgem i915 snd_hda_codec_realtek snd_hda_codec_generic coretemp snd_hda_intel snd_hda_codec r8169 lpc_ich snd_hwdep mii snd_hda_core snd_pcm prime_numbers
[  219.525054] CPU: 1 PID: 14 Comm: cpuhp/1 Tainted: G     U           4.16.0-rc1-g740f57c54ecf-kasan_6+ #1
[  219.525070] Hardware name:  /D510MO, BIOS MOPNV10J.86A.0311.2010.0802.2346 08/02/2010
[  219.525294] RIP: 0010:intel_runtime_pm_get_if_in_use+0xe3/0x150 [i915]
[  219.525313] RSP: 0018:ffff880018f5edf8 EFLAGS: 00010286
[  219.525344] RAX: dffffc0000000008 RBX: ffff880007fc0000 RCX: 0000000000000000
[  219.525361] RDX: 0000000000000001 RSI: ffffffff850609c0 RDI: ffffffff872992a0
[  219.525377] RBP: 0000000000000000 R08: 0000000000000001 R09: 0000000000000000
[  219.525394] R10: 0000000000000000 R11: 0000000000000000 R12: ffff880007fc0000
[  219.525411] R13: ffff880018f5f0f8 R14: ffff880007fc8de8 R15: ffff880018f5f0f0
[  219.525429] FS:  0000000000000000(0000) GS:ffff880019c80000(0000) knlGS:0000000000000000
[  219.525446] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  219.525463] CR2: 0000564df7897e86 CR3: 0000000000d7c000 CR4: 00000000000006e0
[  219.525478] Call Trace:
[  219.525734]  i915_gem_shrink+0x841/0xb50 [i915]
[  219.525802]  ? debug_check_no_locks_freed+0x2a0/0x2a0
[  219.525842]  ? trace_hardirqs_on_thunk+0x1a/0x1c
[  219.526083]  ? i915_gem_shrinker_count+0x2f0/0x2f0 [i915]
[  219.526131]  ? lock_acquire+0x138/0x3c0
[  219.526157]  ? lock_acquire+0x138/0x3c0
[  219.526391]  ? shrinker_lock+0x49/0x210 [i915]
[  219.526465]  ? mutex_trylock+0x15c/0x1a0
[  219.526694]  ? shrinker_lock+0x49/0x210 [i915]
[  219.526969]  ? i915_gem_shrinker_scan+0xc4/0x320 [i915]
[  219.527200]  i915_gem_shrinker_scan+0xc4/0x320 [i915]
[  219.527448]  ? i915_gem_shrinker_vmap+0x3a0/0x3a0 [i915]
[  219.527533]  shrink_slab.part.18+0x2d0/0x8d0
[  219.527613]  ? unregister_shrinker+0x1f0/0x1f0
[  219.527668]  ? mem_cgroup_iter+0x37d/0xc50
[  219.527728]  shrink_node+0x882/0xbe0
[  219.527847]  ? shrink_node_memcg+0x11c0/0x11c0
[  219.527882]  ? mark_held_locks+0xa8/0xf0
[  219.527931]  ? trace_hardirqs_on_caller+0x33f/0x590
[  219.527961]  ? ktime_get+0xad/0x140
[  219.528015]  do_try_to_free_pages+0x2d3/0xd70
[  219.528099]  ? allow_direct_reclaim.part.23+0x1d0/0x1d0
[  219.528132]  ? shrink_node+0xbe0/0xbe0
[  219.528213]  try_to_free_pages+0x1cd/0x570
[  219.528257]  ? do_try_to_free_pages+0xd70/0xd70
[  219.528355]  __alloc_pages_nodemask+0xadf/0x2110
[  219.528423]  ? unwind_next_frame+0x870/0x1970
[  219.528465]  ? deref_stack_reg+0x97/0xc0
[  219.528503]  ? gfp_pfmemalloc_allowed+0x150/0x150
[  219.528539]  ? register_sched_domain_sysctl+0x23a/0x1b90
[  219.528588]  ? unwind_next_frame+0x138/0x1970
[  219.528619]  ? kthread+0x30a/0x3d0
[  219.528677]  ? __read_once_size_nocheck.constprop.4+0x10/0x10
[  219.528698]  ? deref_stack_reg+0xc0/0xc0
[  219.528762]  ? __save_stack_trace+0x6e/0xd0
[  219.528822]  depot_save_stack+0x3bc/0x430
[  219.528870]  kasan_kmalloc+0x142/0x170
[  219.528912]  ? __kmalloc+0xf7/0x340
[  219.528935]  ? register_sched_domain_sysctl+0x23a/0x1b90
[  219.528957]  ? partition_sched_domains+0x4d4/0x840
[  219.528978]  ? sched_cpu_deactivate+0x11b/0x150
[  219.529001]  ? cpuhp_invoke_callback+0x160/0x15f0
[  219.529023]  ? cpuhp_thread_fun+0x35e/0x710
[  219.529044]  ? smpboot_thread_fn+0x50a/0x7f0
[  219.529065]  ? kthread+0x30a/0x3d0
[  219.529086]  ? ret_from_fork+0x24/0x50
[  219.529141]  ? register_sched_domain_sysctl+0x23a/0x1b90
[  219.529169]  ? register_sched_domain_sysctl+0x23a/0x1b90
[  219.529198]  ? set_track+0x87/0x100
[  219.529225]  ? init_object+0x6e/0x80
[  219.529275]  ? ___slab_alloc.constprop.36+0x232/0x3e0
[  219.529303]  ? ___slab_alloc.constprop.36+0x232/0x3e0
[  219.529325]  ? register_sched_domain_sysctl+0x23a/0x1b90
[  219.529410]  ? mark_held_locks+0xa8/0xf0
[  219.529453]  ? register_sched_domain_sysctl+0x23a/0x1b90
[  219.529479]  ? trace_hardirqs_on_caller+0x33f/0x590
[  219.529532]  __kmalloc+0xf7/0x340
[  219.529557]  ? register_sched_domain_sysctl+0x23a/0x1b90
[  219.529604]  register_sched_domain_sysctl+0x23a/0x1b90
[  219.529684]  ? sched_debug_show+0x20/0x20
[  219.529713]  ? debug_object_activate+0x530/0x530
[  219.529771]  ? rcu_lockdep_current_cpu_online+0xdc/0x130
[  219.529802]  ? partition_sched_domains+0x4ae/0x840
[  219.529825]  ? rcu_read_lock_sched_held+0x10f/0x130
[  219.529875]  partition_sched_domains+0x4d4/0x840
[  219.529955]  ? sched_init_domains+0x110/0x110
[  219.529981]  ? __wait_rcu_gp+0x24f/0x390
[  219.530054]  sched_cpu_deactivate+0x11b/0x150
[  219.530086]  ? sched_cpu_activate+0x1e0/0x1e0
[  219.530112]  ? __call_rcu.constprop.53+0x680/0x680
[  219.530132]  ? call_rcu_bh+0x10/0x10
[  219.530166]  ? debug_check_no_locks_freed+0x2a0/0x2a0
[  219.530201]  ? trace_raw_output_rcu_utilization+0xa0/0xa0
[  219.530267]  ? trace_raw_output_rcu_utilization+0xa0/0xa0
[  219.530337]  ? rcu_lockdep_current_cpu_online+0xdc/0x130
[  219.530370]  ? sched_cpu_activate+0x1e0/0x1e0
[  219.530397]  cpuhp_invoke_callback+0x160/0x15f0
[  219.530424]  ? lock_acquire+0x138/0x3c0
[  219.530445]  ? lock_acquire+0x138/0x3c0
[  219.530471]  ? cpuhp_thread_fun+0xaf/0x710
[  219.530507]  ? pci_mmcfg_check_reserved+0x100/0x100
[  219.530565]  cpuhp_thread_fun+0x35e/0x710
[  219.530618]  ? cpuhp_complete_idle_dead+0x10/0x10
[  219.530639]  smpboot_thread_fn+0x50a/0x7f0
[  219.530678]  ? sort_range+0x20/0x20
[  219.530709]  ? __kthread_parkme+0xba/0x1f0
[  219.530739]  ? schedule+0x84/0x1a0
[  219.530768]  ? __kthread_parkme+0xbf/0x1f0
[  219.530805]  ? sort_range+0x20/0x20
[  219.530831]  kthread+0x30a/0x3d0
[  219.530859]  ? _kthread_create_on_node+0xb0/0xb0
[  219.530900]  ret_from_fork+0x24/0x50
[  219.530999] Code: 01 00 00 00 85 c0 74 4a 89 e8 5b 5d c3 80 3d 48 37 4e 00 00 75 f2 89 c6 48 c7 c7 40 f0 61 c0 c6 05 36 37 4e 00 01 e8 ed 2a e1 c2 <0f> ff eb d9 80 3d 3f 37 4e 00 00 75 94 48 c7 c7 60 e8 61 c0 c6
[  219.531880] ---[ end trace 18ec0139488ea0c8 ]---
[  219.607967] IRQ 16: no longer affine to CPU1
[  219.670291] IRQ 24: no longer affine to CPU2
[  219.701489] IRQ 8: no longer affine to CPU3
[  219.701529] IRQ 9: no longer affine to CPU3
[  219.701582] IRQ 18: no longer affine to CPU3
[  219.701640] IRQ 25: no longer affine to CPU3
[  219.743857]  cache: parent cpu1 should not be sleeping
[  219.784549]  cache: parent cpu2 should not be sleeping
[  219.816041]  cache: parent cpu3 should not be sleeping

v2: Add Returns: information to intel_runtime_pm_get_if_in_use() kerneldoc.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180219125046.19363-1-chris@chris-wilson.co.uk
 2018-02-19 15:06:23 +00:00
Chris Wilson
e86584c537 drm: Use idr_init_base(1) when using id==0 for invalid 
Use the new idr_init_base() function to create an IDR that knows id==0
is never allocated as it maps to an invalid identifier. By knowing that
id==0 is invalid, the IDR can start from id=1 instead avoiding the issue
of having to start each lookup from the zeroth leaf as id==0 is always
unused (and thus the tree-of-bitmaps indicate that is the first
available).

References: 6ce711f275 ("idr: Make 1-based IDRs more efficient")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Christian Konig <christian.koenig@amd.com>
Cc: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Christian König <christian.koenig@amd.com> as well.
Link: https://patchwork.freedesktop.org/patch/msgid/20180212145533.30046-1-chris@chris-wilson.co.uk
 2018-02-19 12:21:24 +00:00
Joe Moriarty
a5ef656736 drm: NULL pointer dereference [null-pointer-deref] (CWE 476) problem 
The Parfait (version 2.1.0) static code analysis tool found the
following NULL pointer derefernce problem.

- drivers/gpu/drm/drm_edid.c
The call to drm_cvt_mode() in function drm_mode_std() for the
HDTV hack resulted in the possibility of accessing a NULL pointer
if drm_mode_std() returned NULL.  A check for this added right after
the call to drm_cvt_mode() in this particular area of code.

Signed-off-by: Joe Moriarty <joe.moriarty@oracle.com>
Reviewed-by: Steven Sistare <steven.sistare@oracle.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20180212195144.98323-4-joe.moriarty@oracle.com
 2018-02-19 13:01:20 +01:00