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58674 Commits

Author SHA1 Message Date
Hawking Zhang
7596ab68ff drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10 
To differentiate the mtypes across asics.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
c304b9e519 drm/amdgpu: correct pte mtype field for navi 
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Jack Xiao
367adb2ad5 drm/amdgpu/athub2: enable athub2 clock gating 
Enable athub2 clock gating and light sleep

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
9faa494e2f drm/amdgpu: add flag to support IH clock gating 
Add new flag for IH (interrupt handler) clockgating.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:25:52 -05:00
Hawking Zhang
714ff85251 drm/amdgpu: add new HDP CG flags 
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/
DS (Deep Sleep)/SD (Shut Down) modes are supported. However,
only one of these modes can be enabled at one time.

There is no dynamic power mode switch support. clock/power gating
has to be disabled before making any power mode change.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:25:46 -05:00
Hawking Zhang
54fc447279 drm/amdgpu: create mqd for gfx queues on navi10 
mqd is the memory queue descriptor for gfx and compute.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Jack Xiao
5bfca06928 drm/amdgpu: enable async gfx ring by default 
VDDGFX requires gfx queue to be installed via MAP_QUEUES packet.
Hence, enable async gfx ring by default.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Hawking Zhang
51bcce4621 drm/amdgpu: add module parameter for async_gfx_ring enablement 
0 means disable async_gfx_ring and is the default setting
1 means enable async_gfx_ring

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Hawking Zhang
53b2fe415f drm/amdgpu: enable gfx eop interrupt per gfx pipe 
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Jack Xiao
1919196165 drm/amdgpu/gfx10: add special unmap_queues packet for preemption 
CP introduced a special unmap_queues packet for gfx preemtion.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Hawking Zhang
849aca9f9c drm/amdgpu: Move common code to amdgpu_gfx.c 
move common code to amdgpu_gfx_enable_kcq,so
this function can be shared with gfx8 and gfx9

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Rex Zhu
ba0c13b774 drm/amdgpu: Add common gfx func Disable kcq via kiq 
so can be shared with gfx8 and gfx9

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:21:06 -05:00
Rex Zhu
bc4a6f7135 drm/amdgpu: Add struct kiq_pm4_funcs into kiq struct 
kiq can support 4 pm4 scheduler packets
set_resource, map_queues, unmap_queues, query_status.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:57 -05:00
Hawking Zhang
4fc6a88f01 drm/amdgpu: rename amdgpu_gfx_compute_mqd_sw_init 
The function now will create mqd bos for both gfx queue and compute queue

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:51 -05:00
Hawking Zhang
7470bfcf20 drm/amdgpu: add helper function for gfx queue/bitmap transition 
Similar to what we do for compute already.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:27 -05:00
Hawking Zhang
e537c99461 drm/amdgpu: acquire available gfx queues 
currently, amdgpu will owns the first gfx queue of each pipe
they are:
me:0 pipe:0 queue:0
me:0 pipe:1 queue:0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:17 -05:00
Hawking Zhang
cf02b03f7c drm/amdgpu: add members in amdgpu_me for gfx queue 
Update the structure for gfx10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:02 -05:00
Hawking Zhang
8825af65ff drm/amdgpu/gfx10: new approach to load gfx10 me fw (v4) 
gfx10 allows to only upload me jumptable while save the whole
me image at gtt memory.

v2: program CP_ME_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create me fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:19:56 -05:00
Hawking Zhang
2a00bb1322 drm/amdgpu/gfx10: new approach to load ce fw (v4) 
gfx10 allows to only upload ce jumptable while save the whole
ce image at gtt memory.

v2: program CP_CE_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create ce fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:19:52 -05:00
Hawking Zhang
068ed934ee drm/amdgpu/gfx10: new approach to load pfp fw (v4) 
gfx10 allows to only upload pfp jumptable while save the whole
pfp image at gtt memory.

v2: program CP_PFP_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:19:44 -05:00
Hawking Zhang
225cef9d88 drm/amdgpu: add nbio v2.3 for navi10 (v4) 
nbio handles bus io functionality.

v1: add place holder and initial basic nbio v2.3 functions (Ray)
v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking)
v3: squash in updates (Alex)
v4: whitespace fix (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:18:36 -05:00
Dave Airlie
031e610a6a Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next 
- The coherent memory changes including mm changes.
- Some vmwgfx debug fixes.
- Removal of vmwgfx legacy security checks.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thomas Hellstrom <VMware> <thomas@shipmail.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619072531.4026-1-thomas@shipmail.org
 2019-06-21 12:18:16 +10:00
Leo Liu
b45ddfe811 drm/amdgpu: add nbio callbacks for vcn doorbell support 
For Navi10 VCN2.0, the engine supports Doorbell

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:38 -05:00
Hawking Zhang
09fa0613bd drm/amdgpu: query vram_width from vram_info table 
Driver will get channel_number and channel_width from
vram_info table, then calculate vram_width by multiply
channel_number by channel_width

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:38 -05:00
Hawking Zhang
89d7a79c7b drm/amdgpu: query vram type from atomfirmware vram_info 
vram_type is saved in member vram_module[0].memory_type

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:38 -05:00
Hawking Zhang
98cd7f5b18 drm/amdgpu: add navi pm4 header 
A pm4 header for Navi. PM4 is the packet format used
by the compute and gfx engines.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:38 -05:00
Hawking Zhang
9a87c32fda drm/amdgpu: add sdma v5 packet header file 
Defines the SDMA packet formats.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:38 -05:00
Huang Rui
1f43631be5 drm/amdgpu: add gfx v10 clear state header v2 
Clear state for gfx pipe.

v2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:37 -05:00
Huang Rui
a9833d02b5 drm/amdgpu: add v10 structs header (v2) 
Header for CP structures (MQD, etc.)

V2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:37 -05:00
Hawking Zhang
35c2e91059 drm/amdgpu: parse the new members added by gpu_info ucode v1_1 
Parse the new parameters for gfx10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:16 -05:00
Hawking Zhang
109c80ddb4 drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10 
two new members that specific for navi10 are included in v2_0:
num_sc_per_sh and num_packer_per_sc

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:11 -05:00
Huang Rui
23c6268eb1 drm/amdgpu: add navi10 gpu info firmware 
gpu info firmware stores configuration data for various
IP blocks.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:15:29 -05:00
Hawking Zhang
3e514732c0 drm/amdgpu: add gfx10 specific new member pa_sc_tile_steering_override 
New gfx config parameter.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:15:01 -05:00
Hawking Zhang
02a9e40a83 drm/amdgpu: add gfx10 specific config in amdgpu_gfx_config 
The two members are used to cache the values from gpu_info fw accordingly

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:14:57 -05:00
Hawking Zhang
5228fe3010 drm/amdgpu: Add GDDR6 in vram_name arrary 
For printing vram type.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:14:54 -05:00
Dave Airlie
5eab9cf87b Merge tag 'imx-drm-fixes-2019-06-20' of git://git.pengutronix.de/git/pza/linux into drm-fixes 
drm/imx: ipu-v3 image converter fixes

This series fixes input buffer alignment and downsizer configuration
to adhere to IPU mem2mem CSC/scaler hardware restrictions in certain
downscaling ratios.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://patchwork.freedesktop.org/patch/msgid/1561040798.14349.20.camel@pengutronix.de
 2019-06-21 11:44:24 +10:00
Dave Airlie
91cbf5d236 Merge tag 'drm-intel-fixes-2019-06-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes 
drm/i915 fixes for v5.2-rc6:
- GVT: Fix reserved PVINFO register write (Weinan)
- Avoid clobbering M/N values in fastset fuzzy checks (Ville)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87pnn8sbdp.fsf@intel.com
 2019-06-21 11:39:15 +10:00
Dave Airlie
ea37e1a35c Merge tag 'drm-misc-fixes-2019-06-19' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes 
panfrost- Only unmap BO's if they're mapped (Boris)
core- Handle buffer desc copy_to_user failure properly (Dan)

Cc: Boris Brezillon <boris.brezillon@collabora.com>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619192745.GA145841@art_vandelay
 2019-06-21 11:37:05 +10:00
Dave Airlie
47e3c4c964 Merge branch 'vmwgfx-fixes-5.2' of git://people.freedesktop.org/~thomash/linux into drm-fixes 
A couple of fixes for vmwgfx. Two fixes for a DMA sg-list debug warning
message. These are not cc'd stable since there is no evidence of actual
breakage.
On fix for the high-bandwidth backdoor port which is cc'd stable due to
upcoming hardware, on which the code would otherwise break.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thomas Hellstrom <VMware> <thomas@shipmail.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190618072255.2720-1-thomas@shipmail.org
 2019-06-21 11:28:22 +10:00
Sean Paul
2aa3176725 drm/msm: Re-order uninit function to work during probe defer 
If bind fails, we can call msm_drm_uninit before kms elements have been
created. In this case, drm_atomic_helper_shutdown will fail since there
are no drm objects. Only call drm unregistration and shutdown if drm is
registered.

Also while we're in here move the workqueue destruction to below
component_unbind since components could be actively using the wq during
uninit or in their unbind routine.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190524202919.179289-1-sean@poorly.run
 2019-06-20 17:00:50 -04:00
Huang Rui
852a6626d5 drm/amdgpu: add navi10 asic type 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:56 -05:00
Hawking Zhang
33934b3576 drm/amdgpu: add navi10 ip offset header 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:53 -05:00
Hawking Zhang
76a2d0b0a1 drm/amdgpu: add doorbell assignement for navi10 
Update mappings for Navi10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:51 -05:00
Hawking Zhang
10e4b22735 drm/amdgpu: atomfirmware.h updates for navi10 
Updated tables for Navi10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:48 -05:00
Hawking Zhang
efd8725f03 drm/amdgpu: add navi10 enums header 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:46 -05:00
Hawking Zhang
d2996831b2 drm/amdgpu: add SMUIO 11.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:44 -05:00
Hawking Zhang
3d220cc3bd drm/amdgpu: add OSS 5.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:42 -05:00
Hawking Zhang
f519f0be45 drm/amdgpu: add MMHUB 2.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:39 -05:00
Hawking Zhang
be4008b8c5 drm/amdgpu: add GC 10.1 register headers (v4) 
v2: Update regs (Alex)
v3: More updates (Alex)
v4: more updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:35 -05:00
Hawking Zhang
326354fa97 drm/amdgpu: add VCN 2.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:33 -05:00