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58171 Commits

Author SHA1 Message Date
Jack Xiao
85c90e9b54 drm/amdgpu/mes10.1: upload mes data ucode to gpu buffer 
Allocate GPU buffer and upload mes data ucode to the buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
02b6114948 drm/amdgpu/mes10.1: upload mes ucode to gpu buffer 
Allocate GPU buffer and upload ucode firmware to the buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
086981052b drm/amdgpu/mes10.1: implement ucode CPU buffer destruction 
It implements the CPU buffer destruction of ucode.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
298d05460c drm/amdgpu/mes10.1: load mes firmware file to CPU buffer 
It requests MES firmware binary and uploads to CPU buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
5aa91248c0 drm/amdgpu/mes10.1: add mes firmware info fields 
The newly added fields is to store mes firmware related information.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
7f785e7843 drm/amdgpu/ucode: add mes firmware file support 
The newly added firmware struct is for mes firmware file.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
186b0ca282 drm/amdgpu/ucode: add the definitions of MES ucode and ucode data 
MES requires two seperate firmwares: ucode and ucode data.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
37809f5529 drm/amdgpu/sdma5: incorrect variable type for gpu address 
Incorrect programming with 64bit gpu address assignment for
32bit variable.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
tiancyin
278b6fba22 drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples test 
[why]
When page fault happens, it could lead to sdma hang is RESP_MODE =
0 for non-PRT case.

[how]
Setting  SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt.

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Hawking Zhang
4135f10e26 drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2) 
It's not needed for navi.

v2: remove unused variable (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
6ff687319f drm/amdgpu/nv: set vcn pg flag 
Enable VCN power gating by default.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
6e4cb4e8b3 drm/amdgpu: enable vcn dpm scheme for navi 
On navi1x, vcn dpm scheme was merged into powergating scheme.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
0b8794e252 drm/amdgpu/vcn2: don't access register when power gated 
It will cause bus hang to access register UVD_STATUS
when VCN is in the state of power gated.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Kenneth Feng
a8179d62fb drm/amd/powerplay: add new interface for vcn powergating 
add new interface for vcn powrergating and vcn dpm as well.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Kenneth Feng
c4b76d23df drm/amd/powerplay: enable vcn powergating v2 
enable vcn powergating in driver for navi10

v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
c113ba157f drm/amdgpu/vcn2: notify SMU power up/down VCN 
For sw control power gating, it needs notify SMU to power up/down VCN
when enter/exit working state.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
8a33c4f194 drm/amdgpu/gfx10: fix issues for suspend/resume 
1). use PREEMPT_QUEUE instead of RESET_QUEUE for gfx ring disablement.
2). Need wait for unmapping queue done before continue execution.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Tianci Yin <tianci.yin@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Huang Rui
948f540cd0 drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpm 
This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm
doesn't work so far and we needs to enable the sysfs interfaces.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Kenneth Feng
eb0b49ea40 drm/amd/powerplay: update smu11_driver_if_navi10.h 
update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.15.0

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Xiaojie Yuan
4b6349d4d8 drm/amdgpu/gfx10: fix resume failure when enabling async gfx ring 
'adev->in_suspend' code path is missing in gfx_v10_0_gfx_init_queue()

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Tianci Yin
36f87f0acd drm/amdgpu: disable some gfx light sleep 
temporarily disable to avoid s3 test failure.

s3 test failure log:
"[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout,
signaled seq=8278, emitted seq=8281"

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Tianci Yin
8ea763e230 drm/amdgpu/gfx10: update gfx golden settings 
add new registers: mmCGTT_SPI_CLK_CTRL, mmDB_DEBUG3 and
mmGL2C_CGTT_SCLK_CTRL.

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
8d7315cef9 drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is workable 
This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact
VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Kenneth Feng
4b2bb705a0 drm/amd/powerplay: fix the incorrect type of pptable 
This patch is to fix the incorrect type of pptable, otherwise, the data will be
totally wrong in parsing phase.

Signed-off-by: Kenneth Feng <Kenneth.Feng@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
013fd3a61a drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2) 
This header is actually for each asic, so we should not include in smu_v11_0.c.
And rename the one for navi10.

v2: add hack for XGMI (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
6a36e3e57c drm/amd/powerplay: move getting MAX_FAN_RPM value to asic level 
Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to
asic level.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
8890fe5f43 drm/amd/powerplay: introduce smu power source type to handle AC/DC source for each asic 
This patch introduces new smu power source type, it's to handle the different
AC/DC source defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
973849042e drm/amd/powerplay: move Watermarks_t uses into asic level 
This patch moves the rest of Watermarks_t uses into asic level. It's to avoid
the conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
8b1f4c87a3 drm/amd/powerplay: move SmuMetrics_t uses into asic level 
This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the
conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
ee0db82027 drm/amd/powerplay: move PPTable_t uses into asic level 
This patch moves the rest of PPTable_t uses into asic level. It's to avoid the
conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
cbfba01dde drm/amd/powerplay: use the table size member in the structure instead of getting directly 
This patch uses the table size member in the structure instead of getting
directly, because the table is different in each asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
33bd73ae6c drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the input 
Table id may be different for each asic, so it's good to use this as the input
for common interface.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Alex Deucher
8b2ae145de drm/amd/powerplay/smu11: remove smu_update_table_with_arg 
Nothing was using it.  Just replace with smu_update_table
which is what everything was using via a wrapper anyway.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
22c9c6ca96 drm/amd/powerplay: add tables_init interface for each asic 
The smc tables defines should be in the asic level.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
cdb0c632e4 drm/amd/powerplay: init table_count for smu tables on asic level 
TABLE_COUNT should be inited in asic level. Because the value may be different
on each asic even on the same ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
2436911bdb drm/amd/powerplay: introduce smu table id type to handle the smu table for each asic 
This patch introduces new smu table type, it's to handle the different smu table
defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
ffcb08dfaa drm/amd/powerplay: introduce smu feature type to handle feature mask for each asic 
This patch introduces new smu feature type, it's to handle the different feature
mask defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
0de94acf90 drm/amd/powerplay: introduce smu clk type to handle ppclk for each asic 
This patch introduces new smu clk type, it's to handle the different ppclk
defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Hawking Zhang
54b998ca8d drm/amdgpu: enable sw smu driver for navi10 by default 
Navi10 will use sw smu driver for dynamic power managment,
while vega20 could also use sw smu driver when amdgpu_dpm is
set to 2

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
a899848805 drm/amd/powerplay: enable DCEFCLK dpm support 
Enabale DCEFCLK dpm on navi10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
acbcc111ce drm/amd/powerplay: gfxoff-seperate the Vega20 case 
seperate the Vega20 case from navi10 for gfxoff so that gfxoff
won't be allowed on Vega20

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
9e04021602 drm/amd/amdgpu: fw version check with gfxoff 
1. check the firmware version when enabling gfxoff
2. overwrite the pptable to make sure gfxoff is really
enabled on navi10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
bca325280d drm/amd: add gfxoff support on navi10 
add the gfxoff interface to navi10,it's disabled by default.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
77ee9caf38 drm/amd/powerplay: add allowed feature mask for navi10 
add smu feature mask:
1.FEATURE_DPM_PREFETCHER_BIT
2.FEATURE_DPM_PREFETCHER_BIT
3.FEATURE_ATHUB_PG

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
74c958a376 drm/amd/powerplay: optimization feature mask function for asic 
1.change function return value type: from "unallowed" to "allowed"
2.replace feature mask number with feature macro, the code will clear.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
5586348236 drm/amd/powerplay: remove duplicate code from smu hw init 
remove duplicate code (un-used) in smu

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
b55c83a743 drm/amd/powerplay: implement smc firmware v2.1 for smu11 
1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware.
2.optimization current pptable load framework.
3.rename read_pptable_from_vbios with setup_pptable.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
19d894b92d drm/amd/powerplay: add smu11 smu_if_version check for navi10 
add smu11 fw version check for navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
e17980535b drm/amd/powerplay: move the function of is_dpm_running to asic file 
the function os is_dpm_running is aisc related function,
so move them to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
6d22f1aa92 drm/amd/powerplay: move the function of read_sensor to asic file 
The read_sensor functions has asic related parts code,
so move them to asic file to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00