Pull clkdev updates from Russell King:
"This series addresses some breakage in clkdev caused by a previous
patch set from the clk tree which introduced per-user clk structures.
This basically renamed the existing 'struct clk' to 'struct clk_hw',
and introduced a new 'struct clk'.
This change will break anyone using clk_add_alias() with the common
clk code enabled. Thankfully, the intersection of users of
clk_add_alias() and those using the common clk code is practically
zero, but this is something which should be fixed to keep the code
sane.
The problem is that clk_add_alias() does this:
r = clk_get(...);
l = clkdev_alloc(r, ...);
clk_put(...);
which causes the alias to store a pointer to 'r', which has been
freed.
The original patch set tried to work around this problem incorrectly -
at clk_get() time, it tried to convert the struct clk to a struct
clk_hw, and then creating a new struct clk from that. Clearly, if the
original struct clk has been freed, then we have a use-after-free bug.
We have other places in the tree which do something similar, so this
series also addresses those locations too.
This series addresses this problem by converting clkdev to store and
use the clk_hw pointer. This allows clk_get() to only have to create
it's per-user struct clk from the clk_hw. We can also get to the
desired clk_hw at clk_add_alias() or clk lookup creation time, when
the struct clk is "alive".
We also perform some cleanups of the code:
- replacing looped calls to clkdev_add() with clkdev_add_table()
- replacing open-coded lookup allocation (which should have been
using clkdev_alloc()) and subsequent clkdev_add() with
clkdev_create()
- replacing open-coded clk_add_alias() with clk_add_alias()"
* 'for-linus-clk' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
clk: s2mps11: use clkdev_create()
ASoC: migor: use clkdev_create()
ARM: omap2: use clkdev_add_alias()
ARM: omap2: use clkdev_create()
ARM: orion: use clkdev_create()
ARM: lpc32xx: convert to use clkdev_add_table()
SH: use clkdev_add_table()
clkdev: add clkdev_create() helper
clkdev: const-ify connection id to clk_add_alias()
clkdev: get rid of redundant clk_add_alias() prototype in linux/clk.h
clkdev: drop __init from clkdev_add_table()
clk: update clk API documentation to clarify clk_round_rate()
clkdev: use clk_hw internally
The error handling was a bit messy and buggy. It freed "pll_clock" then
dereferenced it, and then freed it again. I've re-written it in normal
kernel style.
Fixes: 42ff8e8008c8 ('h8300: clock driver')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
The driver supports decoding and statically modelling PLL state (i.e.
we inherit state from bootloader) and provides support for all
peripherals that support simple one-bit gated clocks. The covers all
peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested on an STM32F429I-Discovery board. The clock counts
for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
looks OK when checked with a stopwatch. I have also tested a prototype
driver for the RNG hardware. The RNG clock is correctly enabled by the
framework (also did inverse test and proved that by changing DT to
configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
[sboyd@codeaurora.org: Silence sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.
[ralf@linux-mips.org: Resolve a number of simple conflicts.]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9790/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
clk: tegra: Changes for v4.2-rc1
This contains the EMC clock driver that's been exhaustively reviewed and
tested. It also includes a change to the clock core that allows a clock
provider to perform low-level reparenting of clocks. This is required by
the EMC clock driver because the reparenting needs to be done at a very
specific point in time during the EMC frequency switch.
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210.
Changes by Bartlomiej:
- fixed issue with wrong dividers being setup by Common Clock Framework
(by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock,
without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board), this
was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE
and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in
"[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update
clock flags") but using these flags is not sufficient to fix the issue
observed
- removed Exynos5250 and Exynos5420 support for now
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Changes by Bartlomiej:
- fixed issue with setting lower dividers before the parent clock speed
was lowered (the issue resulted in lockup on Exynos4210 SoC based
Origen board when "ondemand" cpufreq governor was stress tested)
- fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change()
problem by moving cfg_data search outside of the spin locked area
- removed leftover kfree() in exynos_register_cpu_clock() that could
result in dereferencing the NULL pointer on error
- moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover
reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers
- added missing "last chance" checks to wait_until_divider_stable() and
wait_until_mux_stable() (needed in case that IRQ handling took long
time to proceed and resulted in function printing incorrect error
message about timeout)
- moved E4210_CPU_DIV[0,1]() macros just before their only users,
this resulted in moving them from patch #2 to patch #3/6 ("clk:
samsung: exynos4: add cpu clock configuration data and instantiate
cpu clock")
- removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV()
macros for now
- added my Copyrights to drivers/clk/samsung/clk-cpu.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This flag is needed to fix the issue with wrong dividers being setup
by Common Clock Framework when using the new Exynos cpu clock support.
The issue happens because clk_core_set_rate_nolock() calls
clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
a chance to run. In case of Exynos cpu clock support pre/post clock
notifiers are registered for mout_apll clock which is a parent of armclk
cpu clock and dividers are modified in both pre and post clock notifier.
This results in wrong dividers values being later programmed by
clk_change_rate(top). To workaround the problem CLK_RECALC_NEW_RATES
flag is added and it is set for mout_apll clock later so the correct
divider values are re-calculated after both pre and post clock notifiers
had run.
For example when using "performance" governor on Exynos4210 Origen board
the cpufreq-dt driver requests to change the frequency from 1000MHz to
1200MHz and after the change state of the relevant clocks is following:
Without use of CLK_GET_RATE_NOCACHE flag:
fout_apll rate: 1200000000
fout_apll_div_2 rate: 600000000
mout_clkout_cpu rate: 600000000
div_clkout_cpu rate: 600000000
clkout_cpu rate: 600000000
mout_apll rate: 1200000000
armclk rate: 1200000000
mout_hpm rate: 1200000000
div_copy rate: 300000000
div_hpm rate: 300000000
mout_core rate: 1200000000
div_core rate: 1200000000
div_core2 rate: 1200000000
arm_clk_div_2 rate: 600000000
div_corem0 rate: 300000000
div_corem1 rate: 150000000
div_periph rate: 300000000
div_atb rate: 300000000
div_pclk_dbg rate: 150000000
sclk_apll rate: 1200000000
sclk_apll_div_2 rate: 600000000
With use of CLK_GET_RATE_NOCACHE flag:
fout_apll rate: 1200000000
fout_apll_div_2 rate: 600000000
mout_clkout_cpu rate: 600000000
div_clkout_cpu rate: 600000000
clkout_cpu rate: 600000000
mout_apll rate: 1200000000
armclk rate: 1200000000
mout_hpm rate: 1200000000
div_copy rate: 200000000
div_hpm rate: 200000000
mout_core rate: 1200000000
div_core rate: 1200000000
div_core2 rate: 1200000000
arm_clk_div_2 rate: 600000000
div_corem0 rate: 300000000
div_corem1 rate: 150000000
div_periph rate: 300000000
div_atb rate: 240000000
div_pclk_dbg rate: 120000000
sclk_apll rate: 150000000
sclk_apll_div_2 rate: 75000000
Without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board.
This issue was probably meant to be workarounded by use of
CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in
the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk:
samsung: remove unused clock aliases and update clock flags" patch)
but usage of these flags is not sufficient to fix the issue observed.
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Fix the PERIPHERAL_MAX_SHIFT definition (3 instead of 4) and adapt the
round_rate and set_rate logic accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: "Wu, Songjun" <Songjun.Wu@atmel.com>
The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.
Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Jonas Andersson <jonas@microbit.se>
Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU
provides fine grained gating of most clocks present in the SoC.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU
contains several clock generators and output stages that route the
clocks either directly to peripherals or to a Clock Control Unit
(CCU).
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The crypto SRAM, used by the armada 370 cpuidle code to workaround a bug
in the BootROM code, requires the crypto clk to be up and running.
Flag the crypto clk as IGNORE_UNUSED until we add the proper
infrastructure to define the crypto SRAM in the DT and reference the crypto
clk in this SRAM node.
Reported-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The Broadcom Cygnus SoC is architected under the iProc architecture. It
has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied
from an onboard crystal. Cygnus also has various ASIU clocks that are
derived directly from the onboard crystal.
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The clock code under drivers/clk/bcm now contains code for both the
Broadcom mobile SoCs and the iProc SoCs. Change the the makefile
dependency to be under config flag CONFIG_ARCH_BCM that's enabled for
both families of SoCs
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.
SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed as arugments into the generic iProc PLL and
clock setup functions
Derived from code originally provided by Jonathan Richardson
<jonathar@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The clk-nomadik.o is built for ARCH_NOMADIK -- which is bool, and
hence this code is either present or absent. It will never be
modular, so using module_init as an alias for __initcall can be
somewhat misleading.
Fix this up now, so that we can relocate module_init from
init.h into module.h in the future. If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.
Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups. As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
These files are built off of the tristate COMMON_CLK_MAX77686 and
COMMON_CLK_MAX77802 respectively. They also contains modular function
calls so they should explicitly include module.h to avoid compile
breakage during header shuffles done in the future.
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
A recent change to mark parent names as const missed this struct
member so we get warnings like:
drivers/clk/pxa/clk-pxa25x.c:122:2: warning: initialization
discards 'const' qualifier from pointer target type
Fix it.
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* zte/soc:
ARM: zx: Add basic defconfig support for ZX296702
ARM: dts: zx: add an initial zx296702 dts and doc
clk: zx: add clock support to zx296702
dt-bindings: Add #defines for ZTE ZX296702 clocks
It adds a clock driver for zx296702 SoC to register the clock tree to
Common Clock Framework. All the clocks of bus topology and some the
peripheral clocks are ready with this commit. Some missing leaf clocks
for peripherals will be added later when needed.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
The i.MX SoC updates for 4.2:
- Add new SoC i.MX7D support, which integrates two Cortex-A7 and one
Cortex-M4 cores.
- Support suspend from IRAM on i.MX53, so that DDR pins can be set to
high impedance for more power saving during suspend.
- Move i.MX clock drivers from arch/arm/mach-imx to drivers/clk/imx.
- Move i.MX GPT timer driver from arch/arm/mach-imx into
drivers/clocksource.
- A couple of clock driver update for VF610 and i.MX6Q.
- A few random code correction and improvement.
* tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits)
ARM: imx: imx7d requires anatop
clocksource: timer-imx-gpt: remove include of <asm/mach/time.h>
ARM: imx: move timer driver into drivers/clocksource
ARM: imx: remove platform headers from timer driver
ARM: imx: provide gpt device specific irq functions
ARM: imx: get rid of variable timer_base
ARM: imx: define gpt register offset per device type
ARM: imx: move clock event variables into imx_timer
ARM: imx: set up .set_next_event hook via imx_gpt_data
ARM: imx: setup tctl register in device specific function
ARM: imx: initialize gpt device type for DT boot
ARM: imx: define an enum for gpt timer device type
ARM: imx: move timer resources into a structure
ARM: imx: use relaxed IO accessor in timer driver
ARM: imx: make imx51/3 suspend optional
ARM: clk-imx6q: refine sata's parent
ARM: imx: clk-v610: Add clock for I2C2 and I2C3
ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAP
ARM: imx: add imx7d clk tree support
ARM: clk: imx: update pllv3 to support imx7
...
Conflicts:
arch/arm/mach-imx/Kconfig
The debug_node field is only used when DEBUG_FS config is selected,
so declare it only if DEBUG_FS is selected.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently it is not made explicit why clk_fixed_set_rate() can ignore
its arguments and unconditionally return success. Add a comment
to explain this.
We also mark the clk_ops table const since it should never be
modified at runtime.
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-cdce925.c:550: warning: format ‘%u’ expects type
‘unsigned int’, but argument 6 has type ‘size_t’
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds 'CLK_IGNORE_UNUSED' flag to clocks which is required for
operation of secure monitor call (smc). System will hang when it executes 'smc'
with one of those clock is gated. All related clocks must be enabled.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock and parent
clocks becuase 'aclk_g3d' is used to change GPU frequency for DVFS (Dynamic
Voltage Frequency Scaling) feature and adds CLK_IGNORE_UNUSED flags to
'aclk_asyncapbs_g3d'/'aclk_asyncapbm_g3d' clocks to access the SFR
of the MALI device.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
[cw00.choi: Add patch description and add CLK_SET_RATE_PARENT to 'aclk_g3d' clk]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This DIV_CPIF register must be stored when the system is suspended, and must
be restored on system resume. This patch adds the register to the list of
restored registers.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57}
core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to
change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver.
- 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM.
- 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sprinkled all through the platform clock drivers are code like this to
fill the clock parent array:
for (i = 0; i < num_parents; ++i)
parent_names[i] = of_clk_get_parent_name(np, i);
The of_clk_parent_fill() will do the same as the code above, and while
at it, return the number of parents as well since the logic of the
function is to the walk the clock node to look for the parent.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
[sboyd@codeaurora.org: Fixed kernel-doc]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk-meson8b:
clk: meson8b: Add support for Meson8b clocks
clk: meson: Document bindings for Meson8b clock controller
clk: meson: Add support for Meson clock controller
This patch adds support for the basic clocks found on the Amlogic
Meson8b SoCs.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patchset adds the infrastructure for registering and managing the
core clocks found on Amlogic MesonX SoCs. In particular:
- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
