The Kconfig currently controlling compilation of this code is:
drivers/clk/meson/Kconfig:config COMMON_CLK_MESON8B
drivers/clk/meson/Kconfig: bool
...meaning that it currently is not being built as a module by anyone.
However a recent commit added a bunch of modular boilerplate to this
driver.
Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.
Since module_init translates to device_initcall in the non-modular
case, the init ordering remains unchanged with this commit.
Also note that MODULE DEVICE_TABLE/ALIAS are no-op when non-modular.
We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-amlogic@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160704211220.5685-2-paul.gortmaker@windriver.com
This patch changes the compatibility string to match with the smallest
supported chip (EP7209). Since the DT-support for this CPU is not yet
announced, this change is safe.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
SoC related changes for omaps for v4.8 merge window:
- A series of DSS platform_data fixes to prepare for DSS driver changes
- Add tblck clck aliases for PWM
- A series of trivial spelling corrections
- Remove bogus eQEP, ePWM and eCAP hwmod entries
- A series of McBSP sidetone fixes
- Remove QSPI and DSS addresses from hwmod, these come from dts
- Fix RSTST register offset for pruss
- Make ti81xx_rtc_hwmod static
- Remove wrongly defined RSTST offset for PER Domain, note
that the subject for this one wrongly has "dts" in the
subject
- Add support for omap5 and dra7 workaround for 801819
- A series of patches to make kexec work for SMP omaps
* tag 'omap-for-v4.8/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (30 commits)
ARM: OMAP2+: Fix build if CONFIG_SMP is not set
ARM: OMAP4+: Allow kexec on SMP variants
ARM: OMAP4+: Reset CPU1 properly for kexec
ARM: OMAP4+: Prevent CPU1 related hang with kexec
ARM: OMAP4+: Initialize SAR RAM base early for proper CPU1 reset for kexec
ARM: dts: am43xx: Remove wrongly defined RSTST offset for PER Domain
ARM: OMAP: make ti81xx_rtc_hwmod static
ARM: AM43XX: hwmod: Fix RSTST register offset for pruss
ARM: DRA7: hwmod: remove DSS addresses from hwmod
ARM: DRA7: hwmod: Remove QSPI address space entry from hwmod
ARM: OMAP2+: McBSP: Remove the old iclk allow/deny idle code
ASoC: omap-mcbsp: sidetone: Use the new callback for iclk handling
ASoC: omap-mcbsp: Rename omap_mcbsp_sysfs_remove() to omap_mcbsp_cleanup()
ARM: OMAP3: pdata-quirks: Add support for McBSP2/3 sidetone handling
ARM: OMAP3: McBSP: New callback for McBSP2/3 ICLK idle configuration
ARM: OMAP3: hwmod data: Fix McBSP2/3 sidetone data
ARM: AM335x/AM437x: hwmod: Remove eQEP, ePWM and eCAP hwmod entries
ARM: OMAP2+: Fix typo in sdrc.h
ARM: OMAP2+: Fix typo in omap_device.c
ARM: OMAP2+: Fix typo in omap4-common.c
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Device tree changes for omaps for v4.8 merge window:
- PWM binding updates and related dts changes
- OCM RAM updates for dra7
- Enable n900 lirc-rx51 driver
- omap3-gta04 updates for backlight, bma180, itg3200, hmc5843 and wifi
- am335x, am437x and am57xx operating point updates and additions
- am335x-icev2 pca9536 node
- dra72-evm regulator updates
- edma spelling fixes
- am335x and am437x ethernet phy update
- a series of mcbsp updates
- omap3-gta04 eeprom
- dra7 PCIe unit address fix
- stdout-path for beaglebone variants
- crypto accelerator nodes for am335x, am437x and dra7
* tag 'omap-for-v4.8/dt-part1-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (42 commits)
ARM: dts: AM43xx: Add node for RNG
ARM: dts: AM43xx: clk: Add RNG clk node
ARM: dts: DRA7: Add DT node for RNG IP
ARM: dts: DRA7: Add support for SHA IP
ARM: dts: DRA7: Add DT nodes for AES IP
ARM: dts: DRA7: Add DT node for DES IP
ARM: dts: am335x-bone-common: use stdout-path in Beaglebone boards.
ARM: dts: DRA7: fix unit address of second PCIe instance
ARM: dts: omap3-gta04: Add RFID eeprom node
ARM: dts: omap4-duovero: Add pdmclk binding for audio
ARM: dts: omap4-var-som-om44: Add pdmclk binding for audio
ARM: dts: omap4-sdp: Add pdmclk binding for audio
ARM: dts: omap4-panda-common: Add pdmclk binding for audio
ARM: dts: omap5-board-common: Add pdmclk binding for audio
ARM: dts: omap3: Add clocks to McBSP nodes
ARM: dts: am335x-bone-common: Mark MAC as having only one PHY
ARM: dts: am437x-idk-evm: Mark MAC as having only one PHY
ARM: dts: Correct misspelling, "emda3" -> "edma3"
ARM: dts: dra72-evm: Rename 3.3V regulator tag
ARM: dts: am335x-icev2: Add DT node for TI PCA9536
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds the EBI2 2X and EBI2 clocks to the MSM8660/APQ8060
GCC. This is necessary to enable clocking of the external bus
interface so that peripherals on it can be mounted. These two
clocks are simple gated branch clocks.
In the vendor tree clock-8x60, these clocks have some kind of
dependency, the EBI2 clock has .depends = &ebi2_2x_clk.c,
what this means is undocumented, it doesn't seem like there
is a parent/child relationship, so the solution I chose was to
just have the EBI2 driver get and enable both clocks.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Formerly clk core does not support imx7d clock type well that all
its clock operations requires the parent clock on.
Therefore we enabled all clocks by default in clock driver
initialization for other module clocks operate well.
After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE',
clk core can handle such clock type well, so we don't have to enable
them all by default anymore. Instead, we only enable a minimum required
set of clocks.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On Freescale i.MX7D platform, all clocks operations, including
enable/disable, rate change and re-parent, requires its parent clock on.
Current clock core can not support it well.
This patch adding flag CLK_OPS_PARENT_ENABLE to handle this special case in
clock core that enable its parent clock firstly for each operation and
disable it later after operation complete.
The patch part 2 fixes set clock rate and set parent while its parent
is off. The most special case is for set_parent() operation which requires
all parents including both old and new one to be enabled at the same time
during the operation.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@codeaurora.org: Move set_rate tracepoint after prepare_enable]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On Freescale i.MX7D platform, all clocks operations, including
enable/disable, rate change and re-parent, requires its parent
clock enable. Current clock core can not support it well.
This patch introduce a new flag CLK_OPS_PARENT_ENABLE to handle this
special case in clock core that enable its parent clock firstly for
each operation and disable it later after operation complete.
The patch part 1 fixes the possible disabling clocks while its parent
is off during kernel booting phase in clk_disable_unused_subtree().
Before the completion of kernel booting, clock tree is still not built
completely, there may be a case that the child clock is on but its
parent is off which could be caused by either HW initial reset state
or bootloader initialization.
Taking bootloader as an example, we may enable all clocks in HW by default.
And during kernel booting time, the parent clock could be disabled in its
driver probe due to calling clk_prepare_enable and clk_disable_unprepare.
Because it's child clock is only enabled in HW while its SW usecount
in clock tree is still 0, so clk_disable of parent clock will gate
the parent clock in both HW and SW usecount ultimately. Then there will
be a child clock is still on in HW but its parent is already off.
Later in clk_disable_unused(), this clock disable accessing while its
parent off will cause system hang due to the limitation of HW which
must require its parent on.
This patch simply enables the parent clock first before disabling
if flag CLK_OPS_PARENT_ENABLE is set in clk_disable_unused_subtree().
This is a simple solution and only affects booting time.
After kernel booting up the clock tree is already created, there will
be no case that child is off but its parent is off.
So no need do this checking for normal clk_disable() later.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
No function level change, just moving code place.
clk_disable_unused function will need to call clk_core_prepare_enable/
clk_core_disable_unprepare when adding CLK_OPS_PARENT_ENABLE features.
So move it after clk_core_disable_unprepare to avoid adding forward
declared functions later.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This can be useful when clock core wants to enable/disable clocks.
Then we don't have to convert the struct clk_core to struct clk to call
clk_enable/clk_disable which is a bit un-align with exist using.
And after introduce clk_core_{enable|disable}_lock, we can refine
clk_enable and clk_disable a bit.
As well as clk_core_{enable|disable}_lock, we also added
clk_core_{prepare|unprepare}_lock and clk_core_prepare_enable/
clk_core_unprepare_disable for clock core to easily use.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull rockchip clk driver updates from Heiko Stuebner:
Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.
* tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
clk: rockchip: export rk3228 MAC clocks
clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
clk: rockchip: export rk3228 audio clocks
clk: rockchip: include rk3228 downstream muxes into fractional dividers
clk: rockchip: fix incorrect rk3228 clock registers
clk: rockchip: add clock-ids for rk3228 MAC clocks
clk: rockchip: add clock-ids for rk3228 audio clocks
clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
Pull tegra clk driver updates from Thierry Reding:
Fixes and enhancements mostly for Tegra210 clocks that allow DSI and
HDMI to work on Tegra X1. There's also a refactoring, including fixes,
the USB PLL.
* tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Initialize UTMI PLL when enabling PLLU
clk: tegra: Micro-optimize Tegra210 clock setup
clk: tegra: Make sor_safe the parent of dpaux and dpaux1
clk: tegra: Mark timer clock as critical
clk: tegra: Enable sor1 and sor1_src on Tegra210
clk: tegra: Squash sor1 safe/brick/src into a single mux
clk: tegra: Disable spread spectrum on pll_d2
clk: tegra: Fixup post dividers on Tegra210
The only way for a fixed factor clock to change its rate would be to change
its parent rate.
Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms
that were relying on the fact that the parent rate wouldn't change,
introduce a compatible-based whitelist that will allow clocks to opt-in
that flag.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch exports related MAC clocks for dts reference.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The sclk_macphy_50m is confusing, the sclk_mac_extclk describes
a external clock clearly.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch exports related i2s/spdif clocks for dts reference.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Pull i.MX clk driver updates from Shawn Guo:
- A few correction and improvements on pllv3 driver around AV pll clock
rate calculation, parent setting and power bit handling
- Correct i.MX6UL GPT2 clock names
- A couple of minor fixes on i.MX7D clock driver on DRAM clocks
* tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx6ul: fix gpt2 clock names
clk: imx: refine the powerdown bit of clk-pllv3
clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit
clk: imx: fix pll clock parents
clk: imx7d: correct dram pll type
clk: imx7d: correct dram root clk parent select
clk: imx: correct AV PLL rate formula
Before, there was an ordering issue that the clock provider
had been published in hisi_clk_init before it could provide
valid clocks to consumers. hisi_clk_alloc is just used to
allocate memory space for struct hisi_clock_data. It makes
it possible to publish the provider after the clocks are ready.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Cc: Jon Mason <jonmason@broadcom.com>
Cc: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Tested-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers in this driver, allowing us to
move closer to a clear split of consumer and provider clk APIs.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Utilise the new Critical Clock infrastructure to mark clocks which
much not be disabled as CRITICAL.
Clocks are marked as CRITICAL using clk flags. This patch also
ensures flags are peculated through the framework in the correct
manner.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Utilise the new Critical Clock infrastructure to mark clocks which
much not be disabled as CRITICAL.
Clocks are marked as CRITICAL using clk flags. This patch also
ensures flags are peculated through the framework in the correct
manner.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Utilise the new Critical Clock infrastructure to mark clocks which
much not be disabled as CRITICAL.
While we're at it, reduce the coverage of the flex_flags variable,
since it's only really used in a single for() loop.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Move the UTMI PLL initialization code form clk-tegra<chip>.c files into
clk-pll.c. UTMI PLL was being configured and set in HW control right
after registration. However, when the clock init_table is processed and
child clks of PLLU are enabled, it will call in and enable PLLU as
well, and initiate SW enabling sequence even though PLLU is already in
HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status.
Doing the initialization once during pllu_enable means we configure it
properly into HW control.
A side effect of the commonization/localization of the UTMI PLL init
code, is that it corrects some errors that were present for earlier
generations. For instance, in clk-tegra124.c, it used to have:
#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
when the correct shift to use is present in the new version:
#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
which matches the Tegra124 TRM register definition.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
[rklein: Merged in some later fixes for potential deadlocks]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding: coding style bike-shedding, remove unused variable]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Pull support for Renesas R-car M3-W from Geert Uytterhoeven:
Add initial support for the Clock Pulse Generator and Module Standby and
Software Reset modules on the Renesas R-Car M3-W SoC:
- Basic core clocks,
- SCIF2 (console) module clock,
- INTC-AP (GIC) module clock.
* tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: cpg-mssr: Add support for R-Car M3-W
clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code
clk: renesas: Add r8a7796 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Document r8a7796 support
This clk is critical to operation of the SoC and should never be
turned off. Furthermore, there are no consumers of this clk so
let's just delete it so things like eMMC work.
Reported-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: b1e010c073 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only
natural, but also slightly more efficient, to initialize it before its
children. This avoids orphaning the dpaux and dpaux1 clocks only to get
them reparented when the sor_safe clock is registered.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The gxbb clock controller is the primary clock generation unit for the
AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several
PLLs and the usual post-dividers, muxes, dividers and leaf gates that
are fed into various IP blocks in the SoC.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
