Commit Graph

6184 Commits

Author SHA1 Message Date
Stephen Boyd
72ad720795 clk: qcom: Add MSM8960/APQ8064's HFPLLs
Describe the HFPLLs present on MSM8960 and APQ8064 devices.

Acked-by: Rob Herring <robh@kernel.org> (bindings)
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 13:14:45 -07:00
Stephen Boyd
cb546b797a clk: qcom: Add HFPLL driver
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 13:14:40 -07:00
Stephen Boyd
b3f2f10693 clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 13:14:37 -07:00
Anson Huang
341ce3563e clk: imx6q: add mmdc0 ipg clock
i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 11:16:02 -07:00
Anson Huang
09d47620d0 clk: imx6sl: add mmdc ipg clocks
i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 11:15:51 -07:00
Anson Huang
aac7ff2048 clk: imx6sll: add mmdc1 ipg clock
i.MX6SLL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 11:15:44 -07:00
Anson Huang
891f30bf60 clk: imx6sx: add mmdc1 ipg clock
i.MX6SX has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 11:15:32 -07:00
Anson Huang
acc4f98d44 clk: imx6ul: add mmdc1 ipg clock
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 11:15:20 -07:00
Alexandre Belloni
62061d357c clk: at91: move DT compatibility code to its own file
Move all the DT backward compatibility code to its own file so it can be
deleted later.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:45:39 -07:00
Alexandre Belloni
ecd0bf3377 clk: at91: add at91sam9rl PMC driver
Add a driver for the PMC clocks of the at91sam9rl SoC.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[sboyd@kernel.org: Make i signed to fix signedness bug]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:45:19 -07:00
Alexandre Belloni
1eabdc2f9d clk: at91: add at91sam9x5 PMCs driver
Add a driver for the PMC clocks of the at91sam9x5 SoCs

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[sboyd@kernel.org: Make i signed to fix signedness bug]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:45:16 -07:00
Alexandre Belloni
c8923236a2 clk: at91: add at91sam9260 PMC driver
Add a driver for the PMC clocks of the at91sam9260, at91sam9261,
at91am9263 and at91sam9g20 SoCs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[sboyd@kernel.org: Make i signed to fix signedness bug]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:45:12 -07:00
Alexandre Belloni
a2038077de clk: at91: add sama5d2 PMC driver
Add a driver for the PMC clocks of the sama5d2

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[sboyd@kernel.org: Make i signed to fix signedness bug]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:44:53 -07:00
Alexandre Belloni
084b696bb5 clk: at91: add sama5d4 pmc driver
Add a driver for the PMC clocks of the sama5d4

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[sboyd@kernel.org: Make i signed to fix signedness bug]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:44:33 -07:00
Alexandre Belloni
d387ff5427 clk: at91: add new DT lookup function
Add a new DT lookup function to lookup for PMC clocks.

Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the
platforms are converted.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:44:33 -07:00
Alexandre Belloni
b00cd8e419 clk: at91: add pmc_data struct and helpers
Add a new strut to handle references to all the PMC clocks and implement
allocation/free helpers.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:44:33 -07:00
Alexandre Belloni
b2e39dc0bb clk: at91: allow clock registration from C code
Remove static keyword to allow functions to be used from other units. Also
move some struct and function declarations to pmc.h

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[sboyd@kernel.org: Include pmc.h]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:44:25 -07:00
Alexandre Belloni
c1e4580a1d clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated()
Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it
easier to do it from code that is not parsing device tree.

Also, this fixes an issue where the resulting clk_hw can be dereferenced
before being tested for error.

Fixes: 1a1a36d72e ("clk: at91: clk-generated: make gclk determine audio_pll rate")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:44:00 -07:00
Alexandre Belloni
08979ee55a clk: at91: audio-pll: separate registration from DT parsing
Separate registration out of of_sama5d2_clk_audio_pll*_setup to allow other
code to use it.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[sboyd@kernel.org: Include pmc.h]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:43:45 -07:00
Alexandre Belloni
61170a9373 clk: at91: h32mx: separate registration from DT parsing
Separate registration out of of_sama5d4_clk_h32mx_setup to allow other code
to use it.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 09:39:21 -07:00
Alexandre Belloni
6d631027b8 clk: at91: generated: SSCs don't have a gclk
As the SSCs don't have gclk, don't check for their ID to allow them to set
the audio pll rate.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 09:39:20 -07:00
Alexandre Belloni
7fa75007b7 clk: at91: audio-pll: fix audio pmc type
The allocation for the audio pmc is using the size of struct clk_audio_pad
instead of struct clk_audio_pmc. This works fine because the former is
larger than the latter but it is safer to be correct.

Fixes: ("0865805d82d4 clk: at91: add audio pll clock drivers")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 09:39:19 -07:00
Lubomir Rintel
4917fb90ee clk: mmp2: fix the clock id for sdh2_clk and sdh3_clk
A typo that makes it impossible to get the correct clocks for
MMP2_CLK_SDH2 and MMP2_CLK_SDH3.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Fixes: 1ec770d92a ("clk: mmp: add mmp2 DT support for clock driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 09:02:31 -07:00
Anson Huang
0d09e668b7 clk: imx7d: remove CLK_IS_CRITICAL flag for arm_a7_root_clk
i.MX7D uses virtual cpu clock of "arm" clock to be child clock
of "arm_a7_root_clk" and it is with CLK_IS_CRITICAL flag set, so
no need to add CLK_IS_CRITICAL flag for keeping "arm_a7_root_clk"
use count correct, latest clock tree is as below in clk_summary:

pll_arm_main                         1        1        0   792000000          0
      pll_arm_main_bypass            1        1        0   792000000          0
         pll_arm_main_clk            1        1        0   792000000          0
            arm_a7_src               1        1        0   792000000          0
               arm_a7_cg             1        1        0   792000000          0
                  arm_a7_div         1        1        0   792000000          0
                     arm_a7_root_clk       1        1        0   792000000    0
                        arm          1        1        0   792000000

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 08:26:04 -07:00
Anson Huang
ec1893922d clk: imx: cpu clock should be always critical
Add CLK_IS_CRITICAL flag for cpu clock type to
make cpu clock use count correct, as cpu clock
should be always critical.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 08:26:03 -07:00
Enric Balletbo i Serra
665636b294 clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call
Fixes the signedness bug returning '(-22)' on the return type by removing the
sanity checker in rockchip_ddrclk_get_parent(). The function should return
and unsigned value only and it's safe to remove the sanity checker as the
core functions that call get_parent like clk_core_get_parent_by_index already
ensures the validity of the clk index returned (index >= core->num_parents).

Fixes: a4f182bf81 ("clk: rockchip: add new clock-type for the ddrclk")
Cc: stable@vger.kernel.org
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-10-17 15:12:51 +02:00
Greg Kroah-Hartman
c0cff31be7 Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Stephen writes:
  "clk fixes for v4.19-rc8

   One fix for the Allwinner A10 SoC's audio PLL that wasn't properly
   set and generating noise."

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest setting
2018-10-17 13:40:10 +02:00
Gregory CLEMENT
480d99fdc3 clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe
The parent clock is get only to have its name, and then the clock is no
more used, so we can safely free it using clk_put. Furthermore as between
the successful devm_clk_get() and the devm_clk_put() call we don't exit
the probe function in error so I can use non managed version of clk_get()
and clk_put().

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 16:51:03 -07:00
Dong Aisheng
f08c2e2865 clk: add managed version of clk_bulk_get_all
This patch introduces the managed version of clk_bulk_get_all.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:42:49 -07:00
Dong Aisheng
616e45df7c clk: add new APIs to operate on all available clocks
This patch introduces of_clk_bulk_get_all and clk_bulk_x_all APIs
to users who just want to handle all available clocks from device tree
without need to know the detailed clock information likes clock numbers
and names. This is useful in writing some generic drivers to handle clock
part.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:42:48 -07:00
Dong Aisheng
cfdc0411cf clk: bulk: add of_clk_bulk_get()
'clock-names' property is optional in DT, so of_clk_bulk_get() is
introduced here to handle this for DT users without 'clock-names'
specified. Later clk_bulk_get_all() will be implemented on top of
it and this API will be kept private until someone proves they need
it because they don't have a struct device pointer.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Russell King <linux@arm.linux.org.uk>
Reported-by: Shawn Guo <shawnguo@kernel.org>
Tested-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:42:47 -07:00
Stephen Boyd
c8da78e8a1 clk: tegra210: Include size.h for compilation ease
You can't compile this file by itself because it uses SZ_64K from
sizes.h but doesn't include it. Instead it relies on some certain
configuration pulling that in implicitly somewhere else. Just add the
include to make random compile testing easier.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:33:01 -07:00
Joseph Lo
a4dbbceeee clk: tegra: Fixes for MBIST work around
Fix some incorrect data in LVL2 offset and bit mask.

Fixes: e403d00573 ("clk: tegra: MBIST work around for Tegra210")
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:32:06 -07:00
Marcel Ziswiler
923ca13231 clk: tegra: probe deferral error reporting
Actually report the error code from devm_regulator_get() which may as
well just be a probe deferral.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:29:49 -07:00
Anson Huang
febb654849 clk: imx: imx7d: remove clks_init_on array
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:27:08 -07:00
Anson Huang
686b8b8c7f clk: imx: imx7d: remove unnecessary clocks from clks_init_on array
On i.MX7D, IMX7D_NAND_USDHC_BUS_ROOT_CLK is NOT necessary
for system, and IMX7D_AHB_CHANNEL_ROOT_CLK is NOT existing
at all, remove them from clks_init_on array.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:27:08 -07:00
Paul Cercueil
226dfa4726 clk: Add Ingenic jz4725b CGU driver
Add support for the clocks provided by the CGU in the Ingenic JZ4725B
SoC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:19:48 -07:00
Paul Cercueil
0880fb8660 clk: ingenic: Add proper Kconfig entries
Previously, the CGU code corresponding to the SoC for which we're
compiling the kernel was the only one enabled, which made it impossible
to build one kernel that supports them all.

Now, it is possible to select more than one SoC to support.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:19:15 -07:00
Shefali Jain
652f1813c1 clk: qcom: gcc: Add global clock controller driver for QCS404
Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.

Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Co-developed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
[bamse, vkoul: rebase and tidyup for upstream]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Lowercase hex]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:13:54 -07:00
Bjorn Andersson
a3d152e40e clk: qcom: Export clk_alpha_pll_configure()
This is used by the QCS404 GCC driver, export it to allow that driver to
be compiled as a module..

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:09:20 -07:00
Taniya Das
f2a76a2955 clk: qcom: Add Global Clock controller (GCC) driver for SDM660
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of
defines to avoid duplicates]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:06:43 -07:00
Ronald Wahl
0f5cb0e622 clk: at91: Fix division by zero in PLL recalc_rate()
Commit a982e45dc1 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.

Fixes: a982e45dc1 ("clk: at91: PLL recalc_rate() now using cached...")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ronald Wahl <rwahl@gmx.de>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:49:39 -07:00
Manivannan Sadhasivam
c1a3308a06 clk: hisilicon: Add clock driver for Hi3670 SoC
Add clock driver for HiSilicon Hi3670 SoC utilizing HiSilicon's
common clk code.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:47:16 -07:00
Krzysztof Kozlowski
8985167ecf clk: s2mps11: Fix matching when built as module and DT node contains compatible
When driver is built as module and DT node contains clocks compatible
(e.g. "samsung,s2mps11-clk"), the module will not be autoloaded because
module aliases won't match.

The modalias from uevent: of:NclocksT<NULL>Csamsung,s2mps11-clk
The modalias from driver: platform:s2mps11-clk

The devices are instantiated by parent's MFD.  However both Device Tree
bindings and parent define the compatible for clocks devices.  In case
of module matching this DT compatible will be used.

The issue will not happen if this is a built-in (no need for module
matching) or when clocks DT node does not contain compatible (not
correct from bindings perspective but working for driver).

Note when backporting to stable kernels: adjust the list of device ID
entries.

Cc: <stable@vger.kernel.org>
Fixes: 53c31b3437 ("mfd: sec-core: Add of_compatible strings for clock MFD cells")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:45:14 -07:00
Manivannan Sadhasivam
5ddf0cdf93 clk: actions: Add Actions Semi S900 SoC Reset Management Unit support
Add Reset Management Unit (RMU) support for Actions Semi S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:41:53 -07:00
Manivannan Sadhasivam
c4dd4a2eb6 clk: actions: Add Actions Semi S700 SoC Reset Management Unit support
Add Reset Management Unit (RMU) support for Actions Semi S700 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:41:47 -07:00
Manivannan Sadhasivam
09dbde0154 clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support
Add Reset Management Unit (RMU) support for Actions Semi Owl SoCs.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:41:39 -07:00
Manivannan Sadhasivam
3a23eb725b clk: actions: Cache regmap info in private clock descriptor
In order to support the reset controller, regmap info needs to
be cached in the private clock descriptor, owl_clk_desc. Hence,
save that and also make the clock descriptor struct non const.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:40:54 -07:00
Stephen Boyd
a72d785021 clk: ti: Prepare for remove of OF node name
Another patch is going to change this code to use %pOFn for DT node
names. Fix up the code to make this easy to pick this side of the merge
instead of fixing it up in a merge commit later.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 08:39:02 -07:00
Stephen Boyd
9be766274d clk: Clean up suspend/resume coding style
The normal style is to use 'core' for struct clk_core pointers and to
directly access the core pointer from the clk_hw pointer when we're
within the common clk framework. Update the patches to make it a bit
easier to handle.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-11 09:28:13 -07:00