add support for new CSR atlas7 SoC. atlas7 exists V1 and V2 IP.
atlas7 DMAv1 is basically moved from marco, which has never been
delivered to customers and renamed in this patch.
atlas7 DMAv2 supports chain DMA by a chain table, this
patch also adds chain DMA support for atlas7.
atlas7 DMAv1 and DMAv2 co-exist in the same chip. there are some HW
configuration differences(register offset etc.) with old prima2 chips,
so we use compatible string to differentiate old prima2 and new atlas7,
then results in different set in HW for them.
Signed-off-by: Hao Liu <Hao.Liu@csr.com>
Signed-off-by: Yanchang Li <Yanchang.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Support configurable conversion mode through sysfs. So far, the
mode used was low-power, which is enabled by default now. Beside
that, the modes normal and high-speed are selectable as well.
Use the new device tree property which specifies the maximum ADC
conversion clock frequencies. Depending on the mode used, the
available resulting conversion frequency are calculated
dynamically.
Acked-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Pull USB and PHY driver fixes from Greg KH:
"Here are some USB and PHY driver fixes that resolve some reported
regressions. Also in here are some new device ids.
All of the details are in the shortlog and these patches have been in
linux-next with no problems"
* tag 'usb-4.1-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (22 commits)
USB: cp210x: add ID for HubZ dual ZigBee and Z-Wave dongle
usb: renesas_usbhs: Don't disable the pipe if Control write status stage
usb: renesas_usbhs: Fix fifo unclear in usbhsf_prepare_pop
usb: gadget: f_fs: fix check in read operation
usb: musb: fix order of conditions for assigning end point operations
usb: gadget: f_uac1: check return code from config_ep_by_speed
usb: gadget: ffs: fix: Always call ffs_closed() in ffs_data_clear()
usb: gadget: g_ffs: Fix counting of missing_functions
usb: s3c2410_udc: correct reversed pullup logic
usb: dwc3: gadget: Fix incorrect DEPCMD and DGCMD status macros
usb: phy: tahvo: Pass the IRQF_ONESHOT flag
usb: phy: ab8500-usb: Pass the IRQF_ONESHOT flag
usb: renesas_usbhs: Revise the binding document about the dma-names
usb: host: xhci: add mutex for non-thread-safe data
usb: make module xhci_hcd removable
USB: serial: ftdi_sio: Add support for a Motion Tracker Development Board
usb: gadget: f_midi: fix segfault when reading empty id
phy: phy-rcar-gen2: Fix USBHS_UGSTS_LOCK value
phy: omap-usb2: invoke pm_runtime_disable on error path
phy: fix Kconfig dependencies
...
* clk-meson8b:
clk: meson8b: Add support for Meson8b clocks
clk: meson: Document bindings for Meson8b clock controller
clk: meson: Add support for Meson clock controller
APM X-Gene v1 SoC supports its own implementation of MSI, which is not
compliant to GIC V2M specification for MSI Termination.
There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports.
This MSI block supports 2048 MSI termination ports coalesced into 16
physical HW IRQ lines and shared across all 5 PCIe ports.
As there are only 16 HW IRQs to serve 2048 MSI vectors, to support
set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically
allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores). To steer MSI
interrupt to target CPU, MSI vector is moved around these HW IRQs lines.
With this approach, the total MSI vectors this driver supports is reduced
to 256.
[bhelgaas: squash doc, driver, maintainer update]
Signed-off-by: Duc Dang <dhdang@apm.com>
Signed-off-by: Tanmay Inamdar <tinamdar@apm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Using a fixed (by DTS) parent for clocks when turning on the power
domain may introduce issues in other drivers. For example when such
driver changes the parent during runtime and expects that he is the
only place of such change.
Do not rely on DTS providing the fixed parent for such clocks. Instead
before switching domain off, grab a current parent of a clock with
clk_get_parent().
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
This patch adds two boolean properties to FMan Port.
FMan has 3 types of ports:
- 1G ports
By default, all ports support 1G rate
- 10G Ports
Port which use 10G hardware, and configured as 10G
- 10G Best effort ports
Ports which use 1G hardware, configured as 10G, in this case,
the rate is not guaranteed.
The new properties help to distinguish the different type of ports.
Signed-off-by: Igal Liberman <igal.liberman@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds the devicetree documentation for the ZTE
zx296702 I2S audio controller.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch adds the devicetree documentation for the ZTE
zx296702 SPDIF audio controller.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add support for the TI dp83867 Gigabit ethernet phy
device.
The DP83867 is a robust, low power, fully featured
Physical Layer transceiver with integrated PMD
sublayers to support 10BASE-T, 100BASE-TX and
1000BASE-T Ethernet protocols.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Even if not documented in the datasheet, the Armada 370 SoC can actually
gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA
gateclk in the crypto node.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This part just add necessary change to boot imx7d.
Update clock, pinctrl and gpt for imx7d
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Kishon writes:
phy: for 4.2 merge window
*) new Broadcom SATA3 PHY driver for Broadcom STB SoCs
*) new phy API to get PHY by index which is used in EHCI and
OHCI controller drivers
*) support specifying supply at port level used for multi-port PHYs
*) sparse warning fixes in miphy PHYs
*) fix pm_runtime issues in twl4030 driver
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Chanwoo writes:
Update extcon for v4.2
This patchset include the huge update of extcon core and add the new one extcon
driver and fix minor isseu of extcon drivers.
Detailed description for patchset:
1. Update the extcon core.
- Modify the extcon device name on sysfs from device name name to 'extcon[X]'
as following because if same extcon device are included in H/W development board,
the one of the two device driver might be failed on the probe().
: /sys/class/extcon/[device name] -> /sys/class/extcon/extcon[X]
- Use the unique id for external connectors instead of legacy string name.
Previously, extcon used the string name to identify the type of external
connectors. This way have the many potential issues. So, extcon core define the
unique id for each external connectors as following:
enum extcon {
EXTCON_NONE = 0x0,
/* USB external connector */
EXTCON_USB = 0x1,
EXTCON_USB_HOST = 0x2,
/* Charger external connector */
EXTCON_TA = 0x10,
EXTCON_FAST_CHARGER = 0x11,
EXTCON_SLOW_CHARGER = 0x12,
EXTCON_CHARGE_DOWNSTREAM = 0x13,
/* Audio and video external connector */
EXTCON_LINE_IN = 0x20,
EXTCON_LINE_OUT = 0x21,
EXTCON_MICROPHONE = 0x22,
EXTCON_HEADPHONE = 0x23,
...
};
- Update tye prototype of extcon_register_notifier() by using the unique id
(enum extcon) of external connectors.
- Add extcon_get_edev_name() API to get the name of extcon device on extcon
client driver because the name is included in 'struct extcon_dev' and 'struct
extcon_dev' should be handled in only drivers/extcon directory. So. if extcon
client need the name of extcon device, they could use this function.
- Unify the jig/dock and MHL-TA cable name on extcon driver.
: JIG-{USB-ON|USB-OFF|UART-ON|UART-OFF} -> JIG
: Dock-{Smart|Desk|Audio|Card} -> DOCK
: MHL-TA -> TA
- Use the capital letter for the name of all external connectors.
- Remove the optional print_name() function pointer from struct extcon_dev to
maintain the consistent name of extcon device.
2. Add the new extcon-axp288.c extcon driver.
- The extcon-axp288.c driver support for AXP288 PMIC which has the BC1.2
charger detection capability. So this extcon driver can detect the
EXTCON_SLOW_CHARGER, EXTCON_CHARGE_DOWNSTREAM and EXTCON_FAST_CHARGER.
3. Update the extcon-arizona.c driver.
- Add support for selective detection mode when headphone detection.
- Apply HP clamps for WM8280
4. Clean-up the extcon core and drivers.
- Add manufactor information of each extcon device.
- Fix checkpatch warning and minor coding style on extcon.c.c
- Fix build break if GPIOLIB is not enabled on extcon-usb-gpiio.c.
- Set the direction of gpio when calling devm_gpiod_get() on extcon-usb-gpio.c
It turns out that existing U-Boots will dereference NULL pointers
if the device tree does not have cell-index in the portal nodes.
No patch has yet been merged adding device tree nodes for this binding
(except a dtsi that has not yet been referenced), nor has any driver
yet been merged making use of the binding, so it's not too late to
change the binding in order to keep compatibility with existing
U-Boots.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Add DT bindings documentation for lpc3220-timer. This timer is
used as clocksource on many NXP platforms.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found
on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic
interface which gets enabled by almost the same bits as used on
the a31 for the 3rd phy, but not exactly the same bits so we need
a new compatible for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Felipe writes:
usb: patches for v4.2 merge window
- dwc2 adds hibernation support
- preparation for sunxi glue to musb driver
- new ULPI bus
- new ULPI PHY driver for TUSB1210
- musb patches to support multiple DMA engines on same binary
- support for R-Car E2 on renesas_usbhs
Signed-off-by: Felipe Balbi <balbi@ti.com>
Add the missing r8a7778-specific compatible value, which is already in
use since v4.1-rc1.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge "Device Tree changes for Ux500 and ARM SOC" from Linus Walleij:
- Document Snoop Control Unit (SCU) bindings
- Document Ux500 board bindings
- Define the backup RAM in the DBx500 device tree
* tag 'dt-for-armsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: define the backupram in the device tree
ARM: ux500: add board documentation
ARM: scu: document Snoop Control Unit DT bindings
The Allwinner SoCs have a handful of SRAM that can be either mapped to be
accessible by devices or the CPU.
That mapping is controlled by an SRAM controller, and that mapping might
not be set by the bootloader, for example if the device wasn't used at all,
or if we're using solutions like the U-Boot's Falcon Boot.
We could also imagine changing this at runtime for example to change the
mapping of these SRAMs to use them for suspend/resume or runtime memory
rate change, if that ever happens.
These use cases require some API in the kernel to control that mapping,
exported through a drivers/soc driver.
This driver also implement a debugfs file that shows the SRAM found in the
system, the current mapping and the SRAM that have been claimed by some
drivers in the kernel.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The generic RZ CPG compatible value is mandatory, as the driver uses
only this value for matching. Document that this is a fallback that
must be present.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The generic R-Car Gen2 CPG compatible value is mandatory, as the driver
uses only this value for matching. Document that this is a fallback
that must be present.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The generic MSTP gate clocks compatible value is mandatory, as the
driver uses only this value for matching. Document that this is a
fallback that must be present.
Also fix a typo (missing plural "s") in the compatible value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The generic CPG DIV6 clock compatible value is mandatory, as the driver
uses only this value for matching. Document that this is a fallback
that must be present.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
