This patch adds Multi channel support on Renesas R-Car sound.
This patch is tested on Salvator-X board, but it can't use
Multi channel, because supported format is different between
codec chip and R-Car.
Thus, it was tested on board which doesn't mount codec chip,
with oscilloscope.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
The i.MX device tree updates for 4.5:
- New boards support: imx51-ts4800, imx6q-novena, CompuLab imx7d SoM/SBC,
vf610m4-cosmic
- Add ADC device support for imx6ul and imx7d
- Remove config space from PCIe controller ranges property for i.MX6
- Add Vivante GPU nodes for i.MX6
- Add DCU, LCD, and SATA devices for LS1021A
- A series to update Ventana gw5xxx boards getting HDMI and LVDS to work
simultaneously and devices like PWM and SPI added
- Quite a few random cleanups and minor updates
* tag 'imx-dt-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits)
ARM: dts: imx7d: sbc-imx7: add basic board support
ARM: dts: imx7d: cl-som-imx7: add basic module support
ARM: dts: TS-4800: add touchscreen support
ARM: dts: ts-4800: Add LCD support
ARM: dts: imx6q: add Novena board
devicetree: bindings: Add vendor prefix for Kosagi
ARM: dts: TS-4800: use weim IP to map the FPGA
ARM: dts: TS-4800: drop uart rts/cts pin reservations
ARM: dts: imx6: add Vivante GPU nodes
ARM: dts: imx28: add alternate auart4 pinmux
ARM: dts: ls1021a: add sata node to dts
ARM: dts: TS-4800: add basic device tree
of: documentation: add bindings documentation for TS-4800
of: add vendor prefix for Technologic Systems
ARM: dts: imx7d-sdb: add ADC support
ARM: dts: imx7d.dtsi: add ADC support
ARM: dts: vf-colibri: add CAN support
ARM: mxs: dt: cfa10057: fix backlight PWM
ARM: dts: imx6qdl: move GIC to right location in DT
ARM: dts: imx6qdl: add IPU aliases
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Second set of omap device tree changes for v4.5 merge window. This series
updates the EDMA bindings based on the various fixes to split EDMA into
separate independent devices. It also adds support for more devices on the
CompuLab cm-t335 and LogicPD Torpedo boards, and enables the new bindings
for qspi for am437x and dra7. There are also few dra7 regulator fixes, and
change of gpoi-key,wakeup to wakeup-source.
These depend on commit ae0add740c ("dmaengine: edma: DT: Change reserved
slot array from 16bit to 32bit type") already merged into mainline.
* tag 'omap-for-v4.5/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: LogicPD Torpedo: Add Touchscreen Support
ARM: dts: DRA7-EVM: Add regulator-allow-bypass property for ldo9
ARM: dts: DRA72-EVM: Add regulator-allow-bypass property for ldo1 and ldo2
ARM: dts: AM4372: add entry for qspi mmap region
ARM: dts: DRA7: add entry for qspi mmap region
ARM: OMAP2+: LogicPD Torpedo: Revert Duplicative Entries
ARM: OMAP2+: LogicPD Torpedo + Wireless: Add Bluetooth
ARM: OMAP2+: LogicPD Torpedo: Add LCD Type 15 Support
ARM: dts: cm-t335: add support for bluetooth
ARM: dts: cm-t335: add support for DVI/LCD
ARM: dts: cm-t335: add support for I2C GPIO expander
ARM: dts: cm-t335: add support for SBC-T335
ARM: dts: cm-t335: add support for USB0
ARM: dts: omap: replace legacy *,wakeup property with wakeup-source
ARM: dts: am335x: replace gpio-key,wakeup with wakeup-source property
ARM: DTS: am437x: Use the new DT bindings for the eDMA3
ARM: DTS: am33xx: Use the new DT bindings for the eDMA3
dmaengine: edma: DT: Change reserved slot array from 16bit to 32bit type
dmaengine: edma: DT: Change memcpy channel array from 16bit to 32bit type
Signed-off-by: Olof Johansson <olof@lixom.net>
TI wakeup M3 IPC device driver for v4.5 merge window. This driver will
eventually allow am33xx and am437x to support PM with their Cortex-M3
power management processor.
This driver has been waiting to get merged for quite a while but has
had dependencies to the remoteproc that are now out of the way.
* tag 'omap-for-v4.5/wakeup-m3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
soc: ti: Add wkup_m3_ipc driver
Documentation: dt: add bindings for TI Wakeup M3 IPC device
Signed-off-by: Olof Johansson <olof@lixom.net>
Another new soc - the rk3228 quad-core cortex-a7, a new rk3036 board,
support for the efuses on Rockchip socs and some improvements for
rk3288 regulators.
* tag 'v4.5-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add the kylin board for rk3036
ARM: dts: rockchip: add the sdio/sdmmc node for rk3036
ARM: dts: rockchip: fix the pinctrl bias settings for rk3036
ARM: dts: rockchip: add eFuse node for rk3188 SoCs
ARM: dts: rockchip: add eFuse node for rk3066a SoCs
ARM: dts: rockchip: add eFuse config of rk3288 SoC
ARM: dts: rockchip: add rk3228-evb board
ARM: dts: rockchip: add core rk3228 dtsi
clk: rockchip: Add the clock ids of rk3288 eFuses
ARM: dts: rockchip: Fix typo in rk3288 sdmmc card detect pin name
ARM: dts: rockchip: fix voltage ranges for rk3288-evb-act8846 board
ARM: dts: rockchip: move the public part to rk3288-evb common
ARM: dts: rockchip: add 2 regulators for rk3288-evb-act8846
ARM: dts: rockchip: correct the name of REG8 for rk3288-evb-act8846
clk: rockchip: add dt-binding header for rk3228
clk: rockchip: add id for mipidsi sclk on rk3288
Signed-off-by: Olof Johansson <olof@lixom.net>
SMP special case for the rk3036 and addition of the rk3228
quad-core Cortex-A7 cpu.
* tag 'v4.5-rockchip-soc-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: enable support for RK3228 SoCs
ARM: rockchip: use const and __initconst for rk3036 smp_operations
ARM: rockchip: add support smp for rk3036
Signed-off-by: Olof Johansson <olof@lixom.net>
Add regulators to the scpsys binding.
Move the include of the reset contoller to include/dt-bindings/reset.
Add basic support for mt2701 SoC and evaluation board.
* tag 'v4.4-next-dts' of https://github.com/mbgg/linux-mediatek:
dt-bindings: soc: Add supplies for Mediatek SCPSYS unit
ARM: mediatek: DT: Move reset controller constants into common location
ARM: dts: mediatek: add MT2701 basic support
Document: DT: Add bindings for mediatek MT2701 SoC Platform
Signed-off-by: Olof Johansson <olof@lixom.net>
mvebu dt for 4.5 (part 3)
Add dts for the following boards:
- Zyxel NSA325
- PogoPlug series 4
Add GPU support for Dove
Update boolean property to wakeup source for isil
* tag 'mvebu-dt-4.5-3' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada: replace isil, irq2-can-wakeup-machine with wakeup-source property
ARM: dts: enable GPU for SolidRun's Cubox
ARM: dts: dove: add DT GPU support
ARM: mvebu: kirkwood: add PogoPlug series 4 device tree
ARM: mvebu: add kirkwood compatibles for cloudengine boards
ARM: dts: kirkwood: Add DTS for Zyxel NSA325
Signed-off-by: Olof Johansson <olof@lixom.net>
Third Round of Renesas ARM64 Based SoC DT Updates for v4.5
* Enable SATA
* Add salvator-x part number to DT bindings documentation
* Enable all four A57 cores instead of just one
* Enhanced audio support:
- Use CS2000 as AUDIO_CLK_B
- Set ak4613 In/Out pin as single-end
* tag 'renesas-arm64-dt3-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: renesas: r8a7795: fix SATA clock assignment
arm64: dts: salvator-x: Enable SATA controller
arm64: dts: r8a7795: Add SATA controller node
arm64: renesas: r8a7795: add internal delay for i2c IPs
arm64: renesas: salvator-x: Add board part number to DT bindings
arm64: dts: r8a7795: Add pmu device nodes
arm64: dts: r8a7795: Add Cortex-A57 CPU cores
arm64: dts: r8a7795: Add PSCI node
arm64: renesas: salvator-x: use CS2000 as AUDIO_CLK_B
arm64: renesas: salvator-x: set ak4613 In/Out pin as single-end
Signed-off-by: Olof Johansson <olof@lixom.net>
Rockchip clock changes for 4.5 containing
- a new pll-type used on rk3036 and other Cortex-A7 socs
- new clock-trees for rk3036 and rk3228
- switch rk3288 plls to slow mode on reboot
- a bunch of new clock ids
- some more critical clocks
- wrong register offsets for the rk3368 cpuclks
- allowing more than 2 parents for the cpuclk
The UniPhier System Bus is an external bus that connects on-board
devices to the UniPhier SoC. Each bank (chip select) is dynamically
mapped to the CPU-viewed address base via the bus controller. The
bus controller must be configured before any access to the bus.
This driver parses the "ranges" property of the System Bus node and
initialized the bus controller. After the bus becomes ready, devices
below it are populated.
Note:
Each bank can be mapped anywhere in the supported address space;
there is nothing preventing us from assigning bank 0 on 0x42000000,
0x43000000, or anywhere as long as such region is not used by others.
So, the "ranges" is just one possible software configuration, which
does not seem to fit in device tree because device tree is a hardware
description language. However, of_translate_address() requires
"ranges" in every bus node between CPUs and device mapped on the CPU
address space. In other words, "ranges" properties must be statically
defined in device tree. After some discussion, I decided the dynamic
address reassignment by the driver is too bothersome. Instead, the
device tree should provide a reasonable translation setup that the OS
can rely on.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Cortex-A72 has a PMUv3 implementation that is compatible with the PMU
implemented by Cortex-A57.
This patch hooks up the new compatible string so that the Cortex-A57
event mappings are used.
Signed-off-by: Will Deacon <will.deacon@arm.com>
According to commit 2503a5ecd8
"ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore
boards with L220" Some PB11MPCore RealView core tiles have broken
outer_sync.
We got rid of the custom barriers from the machine by disabling
outer sync, but that was just for the boardfile case. We have
to be able to do the same in the device tree case.
Since __l2c_init() is cloning and copying the L2C vtable,
we pass an argument to this function to optionally numb
the outer sync operation if desired, before initializing
the cache.
After this we can set up the cache correctly on the RealView
PB11MPCore. This was tested on a PB11MPCore known to have the
issue. Before this, spurious crashes would occur if we try to
set up the cache properly, after this it boots rock solid.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Like the previous designs, the A80 has a special pin controller for the
critical pins, like the PMIC bus.
Add a driver for this controller.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens: Add A80 compatible strings to bindings doc; fix pin function
names based on v1.3 datasheet; constify of_device_id table]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We want the USB and PHY fixes in here as well to make things easier for
testing and development.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The documentation in l2c2x0.txt is only valid for L2C210/L2C220/L2C310
(also known as PL210/PL220/PL310 and variants). Mention this explicitly.
And add a note why this isn't valid for integrated L2 controllers.
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53.
Reflect this by adapting the file name accordingly.
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Deprecate using phy-omap-control driver to power on/off the PHY,
and use *syscon* framework to do the same. This handles
powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* API to do the same.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Deprecate using phy-omap-control driver to power on/off the PHY and
use *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Maxim Integrated MAX3355E chip integrates a charge pump and comparators to
enable a system with an integrated USB OTG dual-role transceiver to
function as an USB OTG dual-role device. In addition to sensing/controlling
Vbus, the chip also passes thru the ID signal from the USB OTG connector.
On some Renesas boards, this signal is just fed into the SoC thru a GPIO
pin -- there's no real OTG controller, only host and gadget USB controllers
sharing the same USB bus; however, we'd like to allow host or gadget
drivers to be loaded depending on the cable type, hence the need for the
MAX3355 extcon driver. The Vbus status signals are also wired to GPIOs
(however, we aren't currently interested in them), the OFFVBUS# signal is
controlled by the host controllers, there's also the SHDN# signal wired to
a GPIO, it should be driven high for the normal operation.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
[cw00.choi: Add the GPIOLIB dependency]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
block for AHCI SATA3.
This new compatible string, "brcm,bcm7425-sata-phy", may be used for
most MIPS-based platforms of 40nm process technology.
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The USB phys on Rockchip SoCs contain their own internal PLLs to create
the 480MHz needed. Additionally this PLL output is also fed back into the
core clock-controller as possible source for clocks like the GPU or others.
Until now this was modelled incorrectly with a "virtual" factor clock in
the clock controller. The one big caveat is that if we turn off the usb phy
via the siddq signal, all analog components get turned off, including the
PLLs. It is therefore possible that a source clock gets disabled without
the clock driver ever knowing, possibly making the system hang.
Therefore register the phy-plls as real clocks that the clock driver can
then reference again normally, making the clock hirarchy finally reflect
the actual hardware.
The phy-ops get converted to simply turning that new clock on and off
which in turn controls the siddq signal of the phy.
Through this the driver gains handling for platform-specific data, to
handle the phy->clock name association.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
We need custom handling for these two socs in the driver shortly,
so add the necessary compatible values to binding and driver.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
not yet (fully) supported after this commit.
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This patch adds support for runtime ID/VBUS pin detection if
the channel 0 of R-Car gen3 is used. So, we are able to use
the channel as both host and peripheral.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This patch adds support for R-Car generation 3 USB2 PHY driver.
This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
with the HSUSB (USB2.0 peripheral) device. And each channel has
independent registers about the PHYs.
So, the purpose of this driver is:
1) initializes some registers of SoC specific to use the
{ehci,ohci}-platform driver.
2) detects id pin to select host or peripheral on the channel 0.
For now, this driver only supports 1) above.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Pull the GIC related updates from Marc Zyngier:
"Not a lot this time (what a relief!), but an interesting series from
Linus Walleij coming out of his work converting the ARM RealView
platforms to DT, and a couple of mundane fixes."
here is the pull request for the etnaviv DRM driver. It includes the DT bindings
and the driver itself, platform devicetree changes will be merged through the
respective SoC trees. Otherwise it's just a squashed version of the V2 patches
that have been on the list for a while.
* 'drm-etnaviv-next' of git://git.pengutronix.de/git/lst/linux:
MAINTAINERS: add maintainer and reviewers for the etnaviv DRM driver
drm/etnaviv: add initial etnaviv DRM driver
drm/etnaviv: add devicetree bindings
devicetree: add vendor prefix for Vivante Corporation
Device tree bindings for display panels have moved to a new location.
Unfortunately some of the new bindings added recently ended up in the
old location. Move them to their proper place.
Reported-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Reported-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Commit 1f71e8c96f ("drivers: net: cpsw: Add
support for fixed-link PHY") did not parse the "phy-mode" property in
the case of a fixed-link PHY, leaving slave_data->phy_if with its default
of PHY_INTERFACE_MODE_NA(0). This later gets passed to phy_connect() in
cpsw_slave_open(), and eventually to cpsw_phy_sel() where it hits a default
case that configures the MAC for MII mode.
The user visible symptom is that while kernel log messages seem to indicate
that the interface is set up, there is no network communication. Eventually
a watchdog error occurs:
NETDEV WATCHDOG: eth0 (cpsw): transmit queue 0 timed out
Fixes: 1f71e8c96f ("drivers: net: cpsw: Add support for fixed-link PHY")
Signed-off-by: David Rivshin <drivshin@allworx.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Pull MTD fixes from Brian Norris:
"I was holding out on this pull request for a bit, since there are a
few other small issues being discussed that look like 4.4-rc
regressions. Hopefully I can get those stabilized soon, but these are
ready at any rate:
- A little bit of a last-minute change for the device tree "fixed
partition" binding. This is needed because we might want to reuse
the 'partitions' subnode for other sorts of partitioning
descriptions -- e.g., for describing which on-flash partition
format(s) might be used on the system.
- Also tone down a warning message, since it is probably going to
show up on a lot of systems where it should just be ignored"
* tag 'for-linus-20151217' of git://git.infradead.org/linux-mtd:
doc: dt: mtd: partitions: add compatible property to "partitions" node
mtd: ofpart: don't complain about missing 'partitions' node too loudly
