The XUSB pad controller allows PCIe lanes to be controlled individually,
providing fine-grained control over their power state. Previous attempts
at describing the XUSB pad controller in DT had erroneously assumed that
all PCIe lanes were driven by the same PHY, and hence the PCI host
controller would reference only a single PHY.
Moving to a representation of per-lane PHYs requires that the operating
system driver for the PCI host controller have access to the set of PHY
devices that make up the connection of each root port in order to power
up and down all of the lanes as necessary.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
set of lanes that are used for PCIe, SATA and USB.
A binding exists for the XUSB pad controller already, but it turned out
not to be flexible enough to describe all aspects of the controller. In
particular, the addition of XUSB support (for SuperSpeed USB) has shown
that the existing binding is no longer suitable. Mark the old binding
as deprecated and link to the new binding.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 2 and Gen 3. But beyond that its not clear what the
relationship between IP blocks might be. For example, I believe that
r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
descendant of the former or vice versa.
We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.
For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme being adopted for
drivers for Renesas SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 2 and Gen 3. But beyond that its not clear what the
relationship between IP blocks might be. For example, I believe that
r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
descendant of the former or vice versa.
We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.
For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme being adopted for
drivers for Renesas SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add ADE display controller binding doc.
Add DesignWare DSI Host Controller v1.20a binding doc.
v8: None.
v7: Acked by Rob Herring.
v6:
- Cleanup values part of reg and clocks properties.
- Change "pclk_dsi" clock name to "pclk".
v5:
- Remove endpoint unit address of dsi output port.
- Add "hisilicon,noc-syscon" property for ADE NOC QoS syscon.
- Add "resets" property for ADE reset.
v4:
- Describe more specific of clocks and ports.
- Fix indentation.
v3:
- Make ade as the drm master node.
- Use assigned-clocks to set clock rate.
- Use ports to connect display relavant nodes.
v2:
- Move dt binding docs to bindings/display/hisilicon directory.
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
This adds very rudimentary TCON (timing controller for raw LCD displays)
support to enable the bypass mode in order to use the DCU controller on
Freescale/NXP Vybrid SoC's.
Additionally the register clock and pixel clock has been separated, but
are currently still enabled and disabled pairwise.
Other than that, fixes and cleanups accross the driver.
* 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu:
drm/fsl-dcu: increment version and date
drm/fsl-dcu: implement lastclose callback
drm/fsl-dcu: disable output polling on driver unload
drm/fsl-dcu: deallocate fbdev CMA on unload
drm/fsl-dcu: use variable name dev for struct drm_device
drm/fsl-dcu: handle missing panel gracefully
drm/fsl-dcu: detach panel on destroy
drm/layerscape: reduce excessive stack usage
drm/fsl-dcu: add TCON driver
drm/fsl-dcu: use common clock framework for pixel clock divider
drm/fsl-dcu: add extra clock for pixel clock
drm/fsl-dcu: disable clock on initialization failure and remove
Merge "Part two of device tree changes for omaps for v4.7 merge window" from Tony Lindgren:
- Fix few typos for address-cells and interrupt-names
- Update dra7 voltage rail limits
- Update compatible string for pcf8575 for both nxp and ti prefix
- Add omap5 configuration for gpadc
- Update dra7 for qspi to remove pinmux as it needs to be done by
the bootloader in isolation. Also update the qspi for 64MHz
frequency.
- Add support for Baltos ir2110 and ir3220
- Add industrial and commercial grade thermal thresholds for am57xx
* tag 'omap-for-v4.7/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am57xx-idk: Include Industrial grade thermal thresholds
ARM: dts: am57xx-beagle-x15: Include the commercial grade thresholds
ARM: dts: am57xx: Introduce industrial grade thermal thresholds
ARM: dts: am57xx: Introduce commercial grade thermal thresholds
ARM: dts: add DTS for Baltos IR2110
ARM: dts: add DTS for Baltos IR3220
ARM: dts: split am335x-baltos-ir5221 into dts and dtsi files
ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
ARM: dts: dra7x: Remove QSPI pinmux
ARM: dts: omap5-board-common: describe gpadc for Palmas
ARM: dts: twl6030: describe gpadc
ARM: dts: dra7xx: Fix compatible string for PCF8575 chip
ARM: dts: AM57xx/DRA7: Update SoC voltage rail limits to match data sheet
ARM: dts: OMAP36xx: : DT spelling s/#address-cell/#address-cells/
ARM: dts: omap5-cm-t54: DT spelling s/interrupt-name/interrupt-names/
ARM: dts: omap5-board-common: DT spelling s/interrupt-name/interrupt-names/
The phy-handle, phy_id, and fixed-link properties are mutually exclusive,
and only one need be specified. Make this clear in the binding doc.
Also mark the phy_id property as deprecated, as phy-handle should be
used instead.
Signed-off-by: David Rivshin <drivshin@allworx.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Merge "Samsung soc/drivers update for v4.7" from Krzysztof Kozłowski:
This moves Samsung SROM controller code from arm/mach-exynos into to
separate driver under drivers/memory/samsung. In the future this driver
will be re-used on ARM64 Exynos platform.
* tag 'samsung-drivers-exynos-srom-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
memory: samsung: exynos-srom: Add support for bank configuration
ARM: EXYNOS: Remove SROM related register settings from mach-exynos
MAINTAINERS: Add maintainers entry for drivers/memory/samsung
memory: Add support for Exynos SROM driver
dt-bindings: EXYNOS: Add exynos-srom device tree binding
ARM: dts: change SROM node compatible from generic to model specific
Felipe writes:
usb: changes for v4.7 merge window
Here's the big USB Gadget pull request. This time
not as large as usual with only 57 non-merge
commits.
The most important part here is, again, all the work
on dwc3. This time around we're treating all
endpoints (except for control endpoint) exactly the
same. They all have the same amount of TRBs on the
ring, they all treat the ring as an actual ring with
a link TRB pointing to the head, etc.
We're also helping the host side burst (on
SuperSpeed GEN1 or GEN2 at least) for as long as
possible until the endpoint returns NRDY.
Other than this big TRB ring rework on dwc3, we also
have a dwc3-omap DMA initialization fix, some extra
debugfs files to aid in some odd debug sessions and
a complete removal of our FIFO resizing logic.
We have a new quirk for some dwc3 P3 quirk in some
implementations.
The rest is basically non-critical fixes and the
usual cleanups.
Merge "ARM64: DT: Hisilicon hip05 and hip06 updates for 4.7" Wei Xu:
- Fix its node without msi-cells for hip05
- Add nor flash node for hip05 D02 board
- Add initial dts for hip06 D03 board
- Reorder and add the hip06 D03 binding in the binding document
* tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
Documentation: arm64: Add Hisilicon Hip06 D03 dts binding
arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
arm64: dts: hip05: Add nor flash support
arm64: dts: hip05: fix its node without msi-cells
Merge "NXP LPC32xx device tree updates for v4.7" from Vladimir Zapolskiy:
This includes a few functional changes:
* new representation of MIC, SIC1 and SIC2 interrupt controllers,
* disabled by default SPI1, SPI2, SSP0 and SSP1 SPI controllers in
shared lpc32xx.dtsi file,
* added clock sources for SPI1 and SPI2,
* set default clock rate of HCLK PLL to main osc rate multiplied by 16.
Also there are some non-functional changes:
* flatten board DTS files by exploiting device node labels,
* add 'partitions' device node for NAND SLC / MTD OF,
* correct Atmel vendor prefix to describe on board AT24 EEPROMs,
* rename board DTS files by adding SoC name prefix.
Since now DTS files of LPC32xx boards match "^lpc32[2345]0-" pattern.
* tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx:
ARM: dts: lpc32xx: phy3250: add SoC name prefix to board dts file
ARM: dts: lpc32xx: phy3250: add NAND partitions device node
ARM: dts: lpc32xx: phy3250: avoid extension of device nodes by absolute path
ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file
ARM: dts: lpc32xx: ea3250: fix Atmel at24 eeprom vendor
ARM: dts: lpc32xx: ea3250: add NAND partitions device node
ARM: dts: lpc32xx: ea3250: avoid extension of device nodes by absolute path
ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default
ARM: dts: phy3250: enable ssp0
ARM: dts: lpc32xx: add clock properties to spi nodes
ARM: dts: lpc32xx: set default clock rate of HCLK PLL
The display pipeline of the Allwinner A10 is involving several loosely
coupled components.
Add a documentation for the bindings.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
NXP LPC32xx has three interrupt controllers, namely root Main
Interrupt Controller (MIC) and two supplementary Sub Interrupt
Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
are connected to MIC.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Minor overlapping changes in the conflicts.
In the macsec case, the change of the default ID macro
name overlapped with the 64-bit netlink attribute alignment
fixes in net-next.
Signed-off-by: David S. Miller <davem@davemloft.net>
Pull i2c fixes from Wolfram Sang:
"I2C has one buildfix, one ABBA deadlock fix, and three simple 'add ID'
patches"
* 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: exynos5: Fix possible ABBA deadlock by keeping I2C clock prepared
i2c: cpm: Fix build break due to incompatible pointer types
i2c: ismt: Add Intel DNV PCI ID
i2c: xlp9xx: add support for Broadcom Vulcan
i2c: rk3x: add support for rk3228
Pull ARC fixes from Vineet Gupta:
- lockdep now works for ARCv2 builds
- enable DT reserved-memory binding (for forthcoming HDMI driver)
* tag 'arc-4.6-rc6-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: add support for reserved memory defined by device tree
ARC: support generic per-device coherent dma mem
Documentation: dt: arc: fix spelling mistakes
ARCv2: Enable LOCKDEP
Even if the Armada 37xx does not any specific setup, the device tree
binding documentation requires to use a SoC-specific version
corresponding to the platform first followed by the generic version.
This patch introduce this new compatible string and updates the
documentation accordingly.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Texas Instruments TAS5720L/M device is a high-efficiency mono
Class-D audio power amplifier optimized for high transient power
capability to use the dynamic power headroom of small loudspeakers.
Its digital time division multiplexed (TDM) interface enables up to
16 devices to share the same bus.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
DSPI driver support the register on the controller with big endian
mode R/W. But not use the regmap API.
So update the binding documentation for "big-endian".
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip06 D03 board.
Meanwhile, reorder the soc/board name alphabetically.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Pull ARM SoC fixes from Arnd Bergmann:
"Here are the latest bug fixes for ARM SoCs, mostly addressing recent
regressions. Changes are across several platforms, so I'm listing
every change separately here.
Regressions since 4.5:
- A correction of the psci firmware DT binding, to prevent users from
relying on unintended semantics
- Actually getting the newly merged clock driver for some OMAP
platforms to work
- A revert of patches for the Qualcomm BAM, these need to be reworked
for 4.7 to avoid breaking boards other than the one they were
intended for
- A correction for the I2C device nodes on the Socionext Uniphier
platform
- i.MX SDHCI was broken for non-DT platforms due to a change with the
setting of the DMA mask
- A revert of a patch that accidentally added a nonexisting clock on
the Rensas "Porter" board
- A couple of OMAP fixes that are all related to suspend after the
power domain changes for dra7
- On Mediatek, revert part of the power domain initialization changes
that broke mt8173-evb
Fixes for older bugs:
- Workaround for an "external abort" in the omap34xx suspend/resume
code.
- The USB1/eSATA should not be listed as an excon device on
am57xx-beagle-x15 (broken since v4.0)
- A v4.5 regression in the TI AM33xx and AM43XX DT specifying
incorrect DMA request lines for the GPMC
- The jiffies calibration on Renesas platforms was incorrect for some
modern CPU cores.
- A hardware errata woraround for clockdomains on TI DRA7"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
drivers: firmware: psci: unify enable-method binding on ARM {64,32}-bit systems
arm64: dts: uniphier: fix I2C nodes of PH1-LD20
ARM: shmobile: timer: Fix preset_lpj leading to too short delays
Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"
ARM: dts: r8a7791: Don't disable referenced optional clocks
Revert "ARM: OMAP: Catch callers of revision information prior to it being populated"
ARM: OMAP3: Fix external abort on 36xx waking from off mode idle
ARM: dts: am57xx-beagle-x15: remove extcon_usb1
ARM: dts: am437x: Fix GPMC dma properties
ARM: dts: am33xx: Fix GPMC dma properties
Revert "soc: mediatek: SCPSYS: Fix double enabling of regulators"
ARM: mach-imx: sdhci-esdhc-imx: initialize DMA mask
ARM: DRA7: clockdomain: Implement timer workaround for errata i874
ARM: OMAP: Catch callers of revision information prior to it being populated
ARM: dts: dra7: Correct clock tree for sys_32k_ck
ARM: OMAP: DRA7: Provide proper class to omap2_set_globals_tap
ARM: OMAP: DRA7: wakeupgen: Skip SAR save for wakeupgen
Revert "dts: msm8974: Add dma channels for blsp2_i2c1 node"
Revert "dts: msm8974: Add blsp2_bam dma node"
ARM: dts: Add clocks for dm814x ADPLL
Jonathan writes:
2nd set of new device support, features and cleanup for IIO in the 4.7 cycle.
Bit of a bumper set for new drivers but plenty of other stuff here as well!
New device support
* ad5592R ADC/DAC
- new driver supporting ad5592r and ad5593r combined ADC/DAC and gpio chips.
* Aosong am2315 relative humidity
- new driver with triggered buffer support in follow up patch.
* bmi160 imu
- new driver
* bmp280
- bmp180 support - note there is support in the misc/bmp085 driver. Intent
is to remove that driver long term.
* invensense mpu6050
- cleanup leading to explicit support of mpu9150 with a good few cleanups
along the way.
* Hope RF hp03 pressure and temperature sensor.
- new driver
* maxim DS1803 potentiometer
- new driver
* maxim max44000 light and proximity sensor
- new driver built in a series of steps to support pretty much everything.
* ROHM BH1780 light sensor
- new driver. There is an existing driver in misc that this is pretty much
intended to replace. The discussion on whether to support the non standard
interface of that driver is some way is continuing.
* st-gyro
- lsm9ds0-gyro. The accel/magn side of this will take a while longer as
extensions to the st library are needed for cases where two types of sensor
share a single i2c address.
* ti-adc081c
- support the adc101c and adc121c
* Vishay VEML6070 UV sensor
- new driver.
New features
* core
- devm_ APIs for channel_get and channel_get_all. The first user of these
is the generic ADC based thermal driver. As it is going through the
thermal tree these will be picked up as a patch to that next cycle as that
is how the author preferred to do it.
- mounting matrix support. This new core support allows devices to provide
to userspace (typically from the device tree) allowing compensation for how
the sensor is mounted on the device. First examples are on UAVs but it
has a more mundane use on typical phone where the chip may be on the front
or the back of the circuit board and soldered at any angle. Includes
support for this ABI in ak8975 (which has an older interface, now
deprecated) and mpu6050.
* tools
- add a -a option to enable all available channels in generic_buffer sample.
Makes it somewhat easier to use.
* adis library and drivers
- support manual self test flag clearing. This has technically been broken
for a very long time - result is an offset on readings as the applied field
is on all the time.
* ak8975
- triggered buffer support
* bmc150
- spi support (including splitting the driver into core and i2c parts)
* bmp280
- oversampling support.
* dht11
- improved logging - useful to debug timing issues on this quirky device.
* st-sensors
- read each channel invidivually as not all support the optimization of
reading in bulk. This is technically a fix, but will need to be backported
if desired.
- support open drain and shared interrupts.
* ti-adc081c
- triggered buffer support.
Cleanups
* inkern
- white space fix.
* ad7606
- use the iio_device_claim_direct_mode call rather than open coding equiv.
* ad799x
- white space fix.
* ad9523
- unsigned -> unsigned int
* apds9660
- brace location tidying up.
- silence an uninitialized variable warning.
* ak8975
- else and brace on same line fix.
* at91_adc
- white space fixes.
* bmc150
- use regmap stored copy of the device pointer rather than having an
additional copy.
* bmg160
- use regmap stored copy of the device pointer rather than having an
additional copy.
* hid-sensors
- white space fixes.
* mcp3422
- white space fix.
* mma7455
- use regmap to retrieve the device struct rather than carrying another copy
in the private data.
* ms_sensors
- white space fix.
* mxs-lradc
- move current bindings out of staging - some will be shortly deprecated but
the reality is that we have device trees out there using them so they will
need to be supported for some time. They accidentally got left behind
when the driver graduated from staging.
- white space cleanup.
- set INPUT_PROP_DIRECT.
- move ts config into a better function.
- move the STMP reset out of the ADC init.
* vf610_adc
- case label indenting fix.
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
IO-domain handling is part of the general register files, so should live
under the grf directly. This change allows the grf to be a simple-mfd and
the io-domains fetching the syscon regmap from that parent-node.
The old binding is of course preserved, though deprecated.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit adds the Device Tree binding documentation that allows to
describe the PCIe controller found in Marvell Armada 7K/8K SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <rob@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
GM20B's definition is mostly similar to GK20A's, but requires an
additional clock.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Merge "ARM: dts: Add OXNAS Platform Bindings" from Neil Armstrong:
* tag 'ox810se-arm-dt-v4.6-rc3' of https://github.com/superna9999/linux:
ARM: boot: dts: Add Western Digital My Book World Edition device tree
dt-bindings: Add Western Digital to vendor prefixes
dt-bindings: Add OXNAS bindings
ARM: boot: dts: Add Oxford Semiconductor OX810SE dtsi
dt-bindings: Add Oxford Semiconductor to vendor prefixes
dt-bindings: irq: arm,versatile-fpga: add compatible string for OX810SE SoC
Currently ARM CPUs DT bindings allows different enable-method value for
PSCI based systems. On ARM 64-bit this property is required and must be
"psci" while on ARM 32-bit systems this property is optional and must
be "arm,psci" if present.
However, "arm,psci" has always been the compatible string for the PSCI
node, and was never intended to be the enable-method. So this is a bug
in the binding and not a deliberate attempt at specifying 32-bit
differently.
This is problematic if 32-bit OS is run on 64-bit system which has
"psci" as enable-method rather than the expected "arm,psci".
So let's unify the value into "psci" and remove support for "arm,psci"
before it finds any users.
Reported-by: Soby Mathew <Soby.Mathew@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Keep the words talking about what a GPIO bank is, but remove the
binding. We have not agreed that this is something we want to have.
Acked-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Merge "Second Round of Renesas ARM Based SoC R-Car SYSC Updates for v4.7" from Simon Horman:
Introduce a DT-based driver for the R-Car System Controller, as found on
Renesas R-Car H1, R-Car Gen2, and R-Car Gen3 SoCs.
* tag 'renesas-rcar-sysc2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (30 commits)
soc: renesas: rcar-sysc: Add support for R-Car H3 power areas
soc: renesas: rcar-sysc: Add support for R-Car E2 power areas
soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas
soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas
soc: renesas: rcar-sysc: Add support for R-Car H2 power areas
soc: renesas: rcar-sysc: Add support for R-Car H1 power areas
soc: renesas: rcar-sysc: Enable Clock Domain for I/O devices
soc: renesas: rcar-sysc: Make rcar_sysc_power_is_off() static
soc: renesas: rcar-sysc: Add DT support for SYSC PM domains
soc: renesas: rcar-sysc: Improve rcar_sysc_power() debug info
soc: renesas: Move pm-rcar to drivers/soc/renesas/rcar-sysc
clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
soc: renesas: Add r8a7795 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7794 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7793 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7791 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7790 SYSC PM Domain Binding Definitions
soc: renesas: Add r8a7779 SYSC PM Domain Binding Definitions
...
Under the OX810SE, this same controller is used as "Reference Peripheral
Specification" Interrupt Controller, so add new compatible string to support
the Oxford Semiconductor OX810SE SoC Interrupt Controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Because debug dsaf port was separated from service dsaf port, this patch
updates the related information of DT binding.
Signed-off-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add driver for the TCON (timing controller) module. The TCON module
is a separate module attached after the DCU (display controller
unit). Each DCU instance has its own, directly connected TCON
instance. The DCU's RGB and timing signals are passing through
the TCON module. TCON can provide timing signals for raw TFT panels
or operate in a bypass mode which leaves all signals unaltered.
The driver currently only supports the bypass mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible for old device trees.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
-The Freescale Management Complex and all associated objects
use message interrupts, and thus an msi-parent is required.
-Define a ranges property to specify the mapping between
the MC address space and the system address space.
-The fsl-mc node may optionally have dpmac sub-nodes that describe
the relationship between the Ethernet MACs which belong to the MC
and the Ethernet PHYs on the system board.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Acked-by: J. German Rivera <German.Rivera@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
