The Aspeed AST2500 SoC contains a number of USB controllers:
* USB 1.1 Host Controller
* USB 2.0 Host Controller (x2)
* USB 2.0 Virtual Hub
* USB 2.0 Device Controller
* USB 1.1 HID Controller
The controllers are exposed via two USB ports with functionality muxed
as required. The following table illustrates the relationships between
the ports and the controllers via the mux function names:
Port | USB Version | USB Mode | Mux Function
------|--------------|--------------|-------------
A | 2.0 | Virtual Hub | USB2AD
A | 2.0 | Host | USB2AH
B | 1.1 | HID | USB11BHID
B | 2.0 | Device | USB2BD
B | 2.0 | Host | USB2BH
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The AST2400 contains several USB controllers:
* USB 1.1 Host Controller
* USB 2.0 Host Controller
* USB 2.0 Virtual Hub
* USB 1.1 HID Controller
Pins for three ports are routed to the three controllers such that:
* Port 1 is a dedicated USB 1.1 host port
* Port 2 is shared between the USB 1.1 host and HID controllers
* Port 3 is shared between the USB 2.0 host and Hub controllers
As the pins for port 1 are fixed function there is no associated mux
function or group described in the bindings. Ports 2 and 3 are muxed as
above, and the table below describes the mapping between pinmux function
names and ports:
Port | USB Version | USB Mode | Mux Function
------|--------------|-----------|-------------
1 | 1.1 | Host | -
2 | 1.1 | Host | USB11H2
2 | 1.1 | HID | USB11D1
3 | 2.0 | Host | USB2H1
3 | 2.0 | Device | USB2D1
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds the remaining pin functions and mux groups.
All unknown and debug functions are omitted. Existing functions
for qpic, sdio, rgmii, rmii, wifi/d are squashed together as
much as possible. And only in case of a clash, the individually
named functions have been kept. The exceptions are:
led0-11
i2s_rx, i2s_tx, i2s_td, i2s_spdif_in, i2s_spdif_out,
smart0-3
Cc: Varadarajan Narayanan <varada@codeaurora.org>
Cc: Ram Chandra Jangir <rjangir@codeaurora.org>
Cc: John Crispin <john@phrozen.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It's add support for cooling device creation to
aspeed-pwm-tacho.
Cooling device could be bound to a thermal zone
for the thermal control.
Signed-off-by: Mykola Kostenok <c_mykolak@mellanox.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Document i2c Device Tree support for RZ/G1[ME]
(also known as r8a774[35]) SoCs. They are compatible with
R-Car Gen2 SoC family. No driver change is required as the
initialisation sequence is currently the same as for the
R-Car Gen2 fallback binding.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Document i2c Device Tree support for RZ/G1[ME]
(also known as r8aA774[35]) SoCs. They are compatible with
R-Car Gen2 SoC family.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
STM32H7 has slightly different triggers than previous versions.
Introduce st,stm32h7-timer-trigger compatible to handle this new variant.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add the documentation for integrated PHY. A boolean property indicates
the PHY is integrated into the same physical package as the Ethernet
MAC. If needed, muxers should be configured to ensure the integrated
PHY is used. The absence of this property indicates the muxers should
be configured so that the external PHY is used.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The bindings were not updated when the sun5i CCU driver was added in
commit 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver").
Signed-off-by: Jonathan Liu <net147@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Adaptrum is a manufacturer of TV White Space (TVWS) wireless
technology. Using dynamic spectrum access to deliver affordable
internet connectivity over non-line-of-sight (NLOS) fixed wireless,
Adaptrum is helping close the digital divide worldwide.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Signed-off-by: Rob Herring <robh@kernel.org>
CAN driver uses the clk_get_rate call to determine the frequency of the
functional clock. OMAP based SoCs do not require the clock property since
hwmod already handles creating a "fck" clock thats accessible to drivers.
However, this isn't the case for 66AK2G which makes the clocks property
require for that SoC.
66AK2G requires a new property. Therefore, update the binding to also make
this property requirement clear. Also clarify that for OMAP based SoCs
ti,hwmod is a required property.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
The Cortex-A35 uses some implementation defined perf events.
The Cortex-A35 derives from the Cortex-A53 core, using the same event mapings
based on Cortex-A35 TRM r0p2, section C2.3 - Performance monitoring events
(pages C2-562 to C2-565).
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The Cortex-A73 uses some implementation defined perf events.
This patch sets up the necessary mapping for Cortex-A73.
Mappings are based on Cortex-A73 TRM r0p2, section 11.9 Events
(pages 11-457 to 11-460).
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Adds support for clearing different sensor groups. OCC inband sensor
groups like CSM, Profiler, Job Scheduler can be cleared using this
driver. The min/max of all sensors belonging to these sensor groups
will be cleared.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The parallel display device tree binding documentation incorrectly lists
the interface-pix-fmt property with underscores ("interface_pix_fmt").
This was never supported by any driver, and the DT example in the same
file always contained the correct spelling ("interface-pix-fmt").
See commit 19022aaae6 ("staging: drm/imx: Add parallel display
support") and commit 2d62da8ebd ("staging: drm/imx: Add devicetree
binding documentation") for reference.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Rob Herring <robh@kernel.org>
STM32 ADC allows each channel to be sampled with a different sampling
time. There's an application note that deals with this: 'How to get
the best ADC accuracy in STM32...' It basically depends on analog input
signal electrical properties (depends on board).
Add optional 'st,min-sample-time-nsecs' property so this can be tuned
in dt.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
As suggested in reviews the requirement of clocks in the 'sound' node
is dropped and instead a leaf clock is used to configure frequency
of the audio root clock PLL. This can work now after the clock tree
definitions have been updated to allow clock rate setting propagation
on the path from the I2S controller up to the EPLL.
This patch also lowers the CODEC master clock frequency so as
to not exceed the maximum allowed 60 MHz at maximum audio sampling
rates.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Saeed Mahameed says:
====================
mlx5-shared-2017-08-07
This series includes some mlx5 updates for both net-next and rdma trees.
From Saeed,
Core driver updates to allow selectively building the driver with
or without some large driver components, such as
- E-Switch (Ethernet SRIOV support).
- Multi-Physical Function Switch (MPFs) support.
For that we split E-Switch and MPFs functionalities into separate files.
From Erez,
Delay mlx5_core events when mlx5 interfaces, namely mlx5_ib, registration
is taking place and until it completes.
From Rabie,
Increase the maximum supported flow counters.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Update the ti,omap-hsmmc.txt to include information about
66AK2G specific mmc controller. Also cleanup the entries
under optional properties to look a bit nicer.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Pull GPIO fixes from Linus Walleij:
- LP87565: set the proper output level for direction_output.
- stm32: fix the kernel build by selecting the hierarchical irqdomain
symbol properly - this happens to be done in the pin control
framework but whatever, it had dependencies to GPIO so we need to
apply it here.
- Select the hierarchical IRQ domain also for Xgene.
- Fix wakeups to work on MXC.
- Fix up the device tree binding on Exar that went astray, also add the
right bindings.
- Fix the unwanted events for edges from the library.
- Fix the unbalanced chanined IRQ on the Tegra.
* tag 'gpio-v4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
gpio: tegra: fix unbalanced chained_irq_enter/exit
gpiolib: skip unwanted events, don't convert them to opposite edge
gpio: exar: Use correct property prefix and document bindings
gpio: gpio-mxc: Fix: higher 16 GPIOs usable as wake source
gpio: xgene-sb: select IRQ_DOMAIN_HIERARCHY
pinctrl: stm32: select IRQ_DOMAIN_HIERARCHY instead of depends on
gpio: lp87565: Set proper output level and direction for direction_output
MAINTAINERS: Add entry for Whiskey Cove PMIC GPIO driver
Pull ARM SoC fixes from Arnd Bergmann:
"This comes a bit later than I planned, and as a consequence is a
larger than it should be.
Most of the changes are devicetree fixes, across lots of platforms:
Renesas, Samsung Exynos, Marvell EBU, TI OMAP, Rockchips, Amlogic
Meson, Sigma Desings Tango, Allwinner SUNxi and TI Davinci.
Also across many platforms, I applied an older series of simple
randconfig build fixes. This includes making the CONFIG_MTD_XIP option
compile again, which had been broken for many years and probably has
not been missed, but it felt wrong to just remove it completely.
The only other changes are:
- We enable HWSPINLOCK in defconfig to get some Qualcomm boards to
work out of the box.
- A few regression fixes for Texas Instruments OMAP2+.
- A boot regression fix for the Renesas regulator quirk.
- A suspend/resume fix for Uniphier SoCs, fixing the resume of the
system bus"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
ARM: dts: tango4: Request RGMII RX and TX clock delays
bus: uniphier-system-bus: set up registers when resuming
ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridge
ARM: shmobile: rcar-gen2: Fix deadlock in regulator quirk
arm64: defconfig: enable missing HWSPINLOCK
ARM: pxa: select both FB and FB_W100 for eseries
ARM: ixp4xx: fix ioport_unmap definition
ARM: ep93xx: use ARM_PATCH_PHYS_VIRT correctly
ARM: mmp: mark usb_dma_mask as __maybe_unused
ARM: omap2: mark unused functions as __maybe_unused
ARM: omap1: avoid unused variable warning
ARM: sirf: mark sirfsoc_init_late as __maybe_unused
ARM: ixp4xx: use normal prototype for {read,write}s{b,w,l}
ARM: omap1/ams-delta: warn about failed regulator enable
ARM: rpc: rename RAM_SIZE macro
ARM: w90x900: normalize clk API
ARM: ep93xx: normalize clk API
ARM: dts: sun8i: a83t: Switch to CCU device tree binding macros
arm64: allwinner: sun50i-a64: Correct emac register size
ARM: dts: sunxi: h3/h5: Correct emac register size
...
On the first revision of the bindings, only the gates + resets were known
in the AO Clock HW, but more registers used to configures AO clock are known
to be spread among the AO register space.
This patch adds a parent node for the entire system control zone for the AO
domain then moves the clock controller as a subnode of the system control
node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Pull "Rockchip dts32 fixes for 4.13" from Heiko Stübner:
Fix for the recently added mali dt support. The example
showed a wrong value, so fix it before it gets copy-pasted
to much.
* tag 'v4.13-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: fix mali gpu node on rk3288
dt-bindings: gpu: drop wrong compatible from midgard binding example
The PPv2.2 unit has several interrupts used for TX completion
notification. This commit updates the Device Tree binding describing
this HW block to mention such interrupts.
While at it, we update the example to use a recent Device Tree
example, that uses interrupts going through the ICU, and not to the
GIC directly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds documentation of device tree bindings for audio DMIC codec.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The patch seprates the DC offset between headphone and headset.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The patch adds the supplements in the dt-binding document for MediaTek
MT7622 SoC with extra SGMII system controller and relevant clock consumers
listed as the requirements for those SoCs equipped with the SGMII circuit.
Also, add the missing binding information for MT7623 SoC here which relies
on the fallback binding of MT2701.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
