Allow more than the default 256 MPIC sources. Allocates a new flag
(MPIC_LARGE_VECTORS) to be used by platform code when instantiating
the mpic.
I picked 11 bits worth right now since it would cover the number of
sources on any hardware I have seen. It can always be increased later
if needed.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Support for PA6T-style PMC registers.
PMCs are completely implementation-dependent on PPC, and PA6T numbers them
differently from the IBM model.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Introduce _SYSDEV_ATTR(), to be used to just define the struct, and not a
named variable with the attribute. Useful for arrays of sysdev_attributes.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Add cputable entries for which type of PMC implementation the processor
has.
I've only filled in the current 64-bit processors, the unfilled default
value will have same behaviour as before so it can be done over time
as needed.
Also tidy up the dummy_perf implementation a bit, aggregating it into
one function with ifdefs instead of several.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Clean up the ctr_read/write a bit. It's currently defined in the
include but only used in one C file each. The only exception is the
classic version, so keep that in the include and define in the C file
as appropriate.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
PS3 interrupt core update:
- Add ps3_alloc_irq() and ps3_free_irq(), to allocate a virtual interrupt
number for an interrupt outlet, which is needed by the PS3 GPU frame
buffer device and audio drivers
Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Change the PS3 irq allocation routines to take an argument indicating which
cpu (processor thread) the interrupt should be serviced on.
The current system configuration favors device interrupts that are serviced
on cpu0, so that is used as the default.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Various fixes for the PS3 repository code:
- Sync signatures of function prototypes and implementations (enum vs.
unsigned int)
- Correct references to `regions' as `registers':
o Correct enum ps3_region_type as enum ps3_reg_type,
o Correct PS3_REGION_TYPE_* as PS3_REG_TYPE_*,
o Correct ps3_repository_find_region() as ps3_repository_find_reg().
- Correct function name in pr_debug() call
- Minor error condition improvements.
Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This add support of the Freescale mpc86xads reference board to
arch/powerpc. Supported SMC1 and SMC2 (UART and serial console), FEC
100Mbps Ethernet, SCC1 Ethernet (10Mbps hdx)
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This covers common CPM access functions, CPM interrupt controller code,
micropatch and a few compatibility things to kee the same driver base
working with arch/ppc. This version is refined with all the comments
(mostly PIC-related) addressed.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: (27 commits)
[IA64] swiotlb abstraction (e.g. for Xen)
[IA64] swiotlb cleanup
[IA64] make swiotlb use bus_to_virt/virt_to_bus
[IA64] swiotlb bug fixes
[IA64] Hook up getcpu system call for IA64
[IA64] clean up sparsemem memory_present call
[IA64] show_mem() for IA64 sparsemem NUMA
[IA64] missing exports hwsw_sync_...
[IA64] virt_to_page() can be called with NULL arg
[IA64] alignment bug in ldscript
[IA64] register memory ranges in a consistent manner
[IA64] Enable SWIOTLB only when needed
[IA64-SGI] Check for TIO errors on shub2 Altix
[IA64] remove bogus prototype ia64_esi_init()
[IA64] Clear IRQ affinity when unregistered
[IA64] fix ACPI Kconfig issues
[IA64] Fix NULL-pointer dereference in ia64_machine_kexec()
[IA64] find thread for user rbs address
[IA64] use snprintf() on features field of /proc/cpuinfo
[IA64] enable singlestep on system call
...
Instead of pinning per-cpu TLB into a DTR, use DTC. This will free up
one TLB entry for application, or even kernel if access pattern to
per-cpu data area has high temporal locality.
Since per-cpu is mapped at the top of region 7 address, we just need to
add special case in alt_dtlb_miss. The physical address of per-cpu data
is already conveniently stored in IA64_KR(PER_CPU_DATA). Latency for
alt_dtlb_miss is not affected as we can hide all the latency. It was
measured that alt_dtlb_miss handler has 23 cycles latency before and
after the patch.
The performance effect is massive for applications that put lots of tlb
pressure on CPU. Workload environment like database online transaction
processing or application uses tera-byte of memory would benefit the most.
Measurement with industry standard database benchmark shown an upward
of 1.6% gain. While smaller workloads like cpu, java also showing small
improvement.
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
It's not efficient to use a per-cpu variable just to store
how many physical stack register a cpu has. Ever since the
incarnation of ia64 up till upcoming Montecito processor, that
variable has "glued" to 96. Having a variable in memory means
that the kernel is burning an extra cacheline access on every
syscall and kernel exit path. Such "static" value is better
served with the instruction patching utility exists today.
Convert ia64_phys_stacked_size_p8 into dynamic insn patching.
This also has a pleasant side effect of eliminating access to
per-cpu area while psr.ic=0 in the kernel exit path. (fixable
for per-cpu DTC work, but why bother?)
There are some concerns with the default value that the instruc-
tion encoded in the kernel image. It shouldn't be concerned.
The reasons are:
(1) cpu_init() is called at CPU initialization. In there, we
find out physical stack register size from PAL and patch
two instructions in kernel exit code. The code in question
can not be executed before the patching is done.
(2) current implementation stores zero in ia64_phys_stacked_size_p8,
and that's what the current kernel exit path loads the value with.
With the new code, it is equivalent that we store reg size 96
in ia64_phys_stacked_size_p8, thus creating a better safety net.
Given (1) above can never fail, having (2) is just a bonus.
All in all, this patch allow one less memory reference in the kernel
exit path, thus reducing syscall and interrupt return latency; and
avoid polluting potential useful data in the CPU cache.
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
* 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jikos/hid:
USB HID: handle multi-interface devices for Apple macbook pro properly
HID: move away from DEBUG defines in favor of CONFIG_HID_DEBUG
USB HID: fix bogus comment in hid_get_class_descriptor()
USB HID: remove hid_find_field_by_usage()
HID: API - fix leftovers of hidinput API in USB HID
HID: hid debug from hid-debug.h to hid layer
hid: force feedback driver for PantherLord USB/PS2 2in1 Adapter
hid: quirk for multi-input devices with unneeded output reports
hid: allow force feedback for multi-input devices
* 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband:
IB/ehca: Remove obsolete prototypes
IB/ehca: Remove use of do_mmap()
RDMA/addr: Handle ethernet neighbour updates during route resolution
IB: Make sure struct ib_user_mad.data is aligned
IB/srp: Don't wait for response when QP is in error state.
IB: Return qp pointer as part of ib_wc
IB: Include <linux/kref.h> explicitly in <rdma/ib_verbs.h>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc: (32 commits)
mmc: tifm: replace kmap with page_address
mmc: sdhci: fix voltage ocr
mmc: sdhci: replace kmap with page_address
mmc: wbsd: replace kmap with page_address
mmc: handle pci_enable_device() return value in sdhci
mmc: Proper unclaim in mmc_block
mmc: change wbsd mailing list
mmc: Graceful fallback for fancy features
mmc: Handle wbsd's stupid command list
mmc: Allow host drivers to specify max block count
mmc: Allow host drivers to specify a max block size
tifm_sd: add suspend and resume functionality
tifm_core: add suspend/resume infrastructure for tifm devices
tifm_7xx1: prettify
tifm_7xx1: recognize device 0xac8f as supported
tifm_7xx1: switch from workqueue to kthread
tifm_7xx1: Merge media insert and media remove functions
tifm_7xx1: simplify eject function
Add dummy_signal_irq function to save check in ISR
Remove unused return value from signal_irq callback
...
This patch adds the definitions used by pfkeyv2 interface for Camellia
cipher algorithm.
Signed-off-by: Noriaki TAKAMIYA <takamiya@po.ntts.co.jp>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Now that all cipher/compression users have switched over to the new
allocation scheme, we can get rid of the compatility defines and use
proper structs for them.
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This patch adds support for multiple frontend types for each backend
algorithm by passing the type and mask through to the backend type
init function.
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The problem was introduced in 2.6.18.3 with the casting of some
36bit-defines (PCI memory) in au1000.h to resource_size_t which may be
u32 or u64 depending on the experimental CONFIG_RESOURCES_64BIT.
With unset CONFIG_RESOURCES_64BIT, the pci-memory cannot be accessed
because the ioremap in arch/mips/au1000/common/pci.c already used the
truncated addresses.
With set CONFIG_RESOURCES_64BIT, things get even worse, because PCI-scan
aborts, due to resource conflict: request_resource() in arch/mips/pci/pci.c
fails because the maximum iomem-address is 0xffffffff (32bit) but the
pci-memory-start-address is 0x440000000 (36bit).
To get pci working again, I propose the following patch:
1. remove the resource_size_t-casting from au1000.h again
2. make the casting in arch/mips/au1000/common/pci.c (it's allowed and
necessary here. The 36bit-handling will be done in __fixup_bigphys_addr).
With this patch pci works again like in 2.6.18.2, the gcc-compile warnings
in pci.c are gone and it doesn't depend on CONFIG_EXPERIMENTAL.
Signed-off-by: Alexander Bigga <ab@mycable.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
CC arch/mips/au1000/common/pci.o
arch/mips/au1000/common/pci.c:42: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c:43: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c:49: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c:50: warning: large integer implicitly truncated to unsigned type
arch/mips/au1000/common/pci.c: In function ‘au1x_pci_setup’:
arch/mips/au1000/common/pci.c:82: warning: ISO C90 forbids mixed declarations and code
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The old code was assuming that min_low_pfn was always 0. This
means that platforms having a big hole at their memory start
paid the price of wasting some memory for the allocation of
unused entries in mem_map[].
This patch prevents this waste.
It introduces PHYS_OFFSET define which is the start of the
physical memory and uses it wherever needed. Specially when
converting physical/virtual addresses into virtual/physical
ones.
Currently all platforms defines PHYS_OFFSET to 0.
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch makes a better usage of these two globals.
'min_low_pfn' is now correctly setup for all configs, which
allow us to rely on it in boot memory code init.
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Current prom_free_prom_memory() implementations are almost same as
free_init_pages(), or no-op. Make free_init_pages() extern (again)
and make prom_free_prom_memory() use it.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Move I8259A_IRQ_BASE from asm/i8259.h to asm/mach-generic/irq.h and
make it really customizable. And remove I8259_IRQ_BASE declared on
some platforms. Currently only NEC_CMBVR4133 is using custom
I8259A_IRQ_BASE value.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds support for the Gateworks Avila Network Platform in
a separate set of setup files to the IXDP425. This is necessary now
that a driver for the Avila CF card slot is available. It also adds
support for a minor variant on the Avila board known as the Loft,
which has a different number of maximum PCI devices.
Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
csum_fold doesn't need two assembly instructions to perform its task,
it can simply add the high and low parts together by rotating by 16
bits, and the carry into the upper-16 bits will automatically happen.
Also, since csum_tcpudp_magic() is just csum_tcpudp_nofold + csum_fold,
use those two functions to achieve this. Also note that there is a
csum_fold() at the end of ip_fast_csum() as well, so use the real
csum_fold() there as well.
Boot tested on Versatile.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the glue for ARM11 SMP oprofile support, which also supports the
performance monitor in the coherency unit.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add abstraction so that the file can be used by environments other than IA64
and EM64T, namely for Xen.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This patch fixes
- marking I-cache clean of pages DMAed to now only done for IA64
- broken multiple inclusion in include/asm-x86_64/swiotlb.h
- missing call to mark_clean in swiotlb_sync_sg()
- a (perhaps only theoretical) issue in swiotlb_dma_supported() when
io_tlb_end is exactly at the end of memory
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>
getcpu system call returns cpu# and node# on which this system call and
its caller are running. This patch hooks up its implementation on IA64.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
While pursuing and unrelated issue with 64Mb granules I noticed a problem
related to inconsistent use of add_active_range. There doesn't appear any
reason to me why FLATMEM versus DISCONTIG_MEM should register memory to
add_active_range with different code. So I've changed the code into a
common implementation.
The other subtle issue fixed by this patch was calling add_active_range in
count_node_pages before granule aligning is performed. We were lucky with
16MB granules but not so with 64MB granules. count_node_pages has reserved
regions filtered out and as a consequence linked kernel text and data
aren't covered by calls to count_node_pages. So linked kernel regions
wasn't reported to add_active_regions. This resulted in free_initmem
causing numerous bad_page reports. This won't occur with this patch
because now all known memory regions are reported by
register_active_ranges.
Acked-by: Mel Gorman <mel@csn.ul.ie>
Signed-off-by: Bob Picco <bob.picco@hp.com>
Acked-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Driver for the PA Semi PWRficient on-chip Ethernet (1/10G)
Basic enablement, will be complemented with performance enhancements
over time. PHY support will be added as well.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
As is pointed out in
http://www.gelato.org/community/view_linear.php?id=1_1036&from=authors&value=Ian%20Wienand#1_1039,
if single step on break instruction, the break fault has higher
priority than the single-step trap. When the break fault handler
is entered, it advances the IP by 1 instruction so break instruction
single-stepping is skipped, actually it is next instruction which
is single stepped.
This patch modifies this, it adds TIF_SINGLESTEP bit for thread
flags, and generate a fake sigtrap when single stepping break
instruction. Test case in attachment can verify this. Any comments
is welcome.
Signed-off-by: bibo, mao <bibo.mao@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
