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2319 Commits

Author SHA1 Message Date
Alex Deucher
bc50ca291e drm/amdgpu/sienna_cichlid: add SMU i2c support (v2) 
Enable SMU i2c bus access for sienna_cichlid asics.

v2: change callback name

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:38:06 -04:00
Alex Deucher
1bc734759f drm/amdgpu/navi1x: add SMU i2c support (v2) 
Enable SMU i2c bus access for navi1x asics.

v2: add missing implementation

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:38:01 -04:00
Alex Deucher
0e0e11e71e drm/amdgpu/swSMU: remove eeprom from the smu i2c handlers (v2) 
The driver uses it for EEPROM access, but it's just an i2c bus.

v2: change the callback name as well.

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:56 -04:00
Alex Deucher
cd65c33c48 drm/amdgpu/vega20: enable the smu i2c bus for all boards 
There is no longer a ras dependency so it's safe to expose
on all boards.

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:53 -04:00
Alex Deucher
a519fd83cf drm/amdgpu: remove eeprom from the smu i2c handlers 
The driver uses it for EEPROM access, but it's just an i2c bus.

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:49 -04:00
Qiu Wenbo
0c56c862e7 drm/amd/powerplay: fix a crash when overclocking Vega M 
Avoid kernel crash when vddci_control is SMU7_VOLTAGE_CONTROL_NONE and
vddci_voltage_table is empty. It has been tested on Intel Hades Canyon
(i7-8809G).

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=208489
Fixes: ac7822b002 ("drm/amd/powerplay: add smumgr support for VEGAM (v2)")
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:40 -04:00
Jiansong Chen
85dec7176b drm/amd/powerplay: retrieve VCN dpm table per instances 
To accommodate VCN instances variance, otherwise it may trigger
smu response error for configuration with less instances.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:40 -04:00
Jiansong Chen
8985adb69f drm/amd/powerplay: update driver if version for navy_flounder 
It's in accordance with pmfw 65.3.0 for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:40 -04:00
Jiansong Chen
9c0551f23e drm/amd/powerplay: fix typos for clk map 
It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:40 -04:00
Evan Quan
d8e0b16d81 drm/amd/powerplay: tag swSMU code layers 
Per designs, the swSMU code is separated into four layers. And the typical
calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c
-> smu_cmn.c. Compile errors will come out for any violations. This can
help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c ->
amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
704759315a drm/amd/powerplay: revise the calling flow on OD table update 
This can eliminate the cross callings and maintain clear
code layer.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
2132672499 drm/amd/powerplay: drop unnecessary message support check 
These messages are known to be supported by all ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
66c868282f drm/amd/powerplay: move SMC message issuing APIs to smu_cmn.c 
Considering they can be shared by all ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
c1b353b7ea drm/amd/powerplay: update the tables init related 
To avoid cross calling and maintain clear code layer.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
caad2613dc drm/amd/powerplay: move table setting common code to smu_cmn.c 
As they are shared by all ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
e7a95eea22 drm/amd/powerplay: maximum code sharing around watermarks setting 
Maximum code sharing.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
a7bae06199 drm/amd/powerplay: move more APIs to smu_cmn.c 
Considering they are shared by all ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
af5ba6d21a drm/amd/powerplay: common API for disabling all features with exception 
We are moving to centralize all feature enablement/support checking and
setting APIs in smu_cmn.c.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
7dbf78051f drm/amd/powerplay: move ppfeature mask setting to smu_cmn.c 
Considering they are shared by all ASICs. And we are moving
to centralize all feature enablement/support checking and
setting APIs in smu_cmn.c.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
28251d726b drm/amd/powerplay: implement smu_cmn_get_enabled_mask() for all ASICs 
Instead of having each for smu v11 and v12.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:38 -04:00
Evan Quan
b4bb3aaf04 drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.c 
Considering it is shared by all ASICs and smu_cmn.c should be
the right place.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Evan Quan
4d942ae349 drm/amd/powerplay: move dpm feature support checking to smu_cmn.c 
Considering it is shared by all ASICs and smu_cmn.c should be
the right place.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Evan Quan
d23c3ccc21 drm/amd/powerplay: move clock dpm enablement check to smu_v11/v12 
As those APIs of smu_v11/v12 are more widely called. And they
need this check also.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Evan Quan
8264ee69f0 drm/amd/powerplay: drop unused code 
Those code were obsoleted by new common API
smu_cmn_to_asic_specific_index().

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Evan Quan
6c339f37f1 drm/amd/powerplay: unify swSMU index to asic specific index mapping 
By this we can drop redundant code.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Evan Quan
22f2447c04 drm/amd/powerplay: widely share the API for data table retrieving 
Considering the data table retrieving can be more widely shared,
amdgpu_atombios.c is the right place.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Jinzhou.Su
443c7f3c36 drm/amdgpu: add read amdgpu_gfxoff status in debugfs 
Add interface for SMU12 device, used by UMR.

v2: fix code style

Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Evan Quan
75bc07e240 drm/amd/powerplay: suppress compile error around BUG_ON 
To suppress the compile error below for "ARCH=arc".
   drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c: In function 'arcturus_fill_eeprom_i2c_req':
>> arch/arc/include/asm/bug.h:22:2: error: implicit declaration of function 'pr_warn'; did you mean 'pci_warn'? [-Werror=implicit-function-declaration]
      22 |  pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
         |  ^~~~~~~
   include/asm-generic/bug.h:62:57: note: in expansion of macro 'BUG'
      62 | #define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while (0)
         |                                                         ^~~
   drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2157:2: note: in expansion of macro 'BUG_ON'
    2157 |  BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Alex Deucher
ff203e3538 drm/amdgpu/smu11: drop code chuck that got accidently re-added 
Seems to be due to a bad merge.  Code was originally added in
commit 5aaa8fff3a ("drm/amd/powerplay: unload mp1 for Arcturus RAS baco reset")
but later removed in commit 7f70443fd8 ("drm/amdgpu: set mp1 state before reload").
but is back again.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:37 -04:00
Jiansong Chen
d51dc61327 drm/amd/powerplay: set VCN1 pg only for sienna_cichlid 
navy_flounder has one VCN instance, and the work around
is to avoid smu reponse error when setting VCN1 pg for
the chip. It is preferred VCN0 and VCN1 are separated
for the pg setting so better power efficiency can be
achieved.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
82121d154a drm/amdgpu/powerplay: add smu support for navy_flounder 
Now navy_flounder will reuse the smu11 driver_if header and ppt
functions for sienna_cichlid. Later navy_flounder can maintain
its own version if the compatibility is broken.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:41 -04:00
Evan Quan
3cd7e415ae drm/amd/powerplay: drop unused code around thermal range setting 
Leftover of previous cleanups.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:46 -04:00
Evan Quan
1e1964b777 drm/amd/powerplay: maximum the code sharing on thermal irq setting 
Put the common code in smu_v11_0.c instead of having one copy each.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:40 -04:00
Evan Quan
0540ecedcb drm/amd/powerplay: sort the call flow on temperature ranges retrieving 
This can help to maintain clear code layer.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:32 -04:00
Evan Quan
e02e4d513e drm/amd/powerplay: cache the software_shutdown_temp 
As it's needed in the succeeding thermal irq setting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:24 -04:00
Evan Quan
2b1f12a2da drm/amd/powerplay: correct Sienna Cichlid temperature limit settings 
These are needed for temp1/2/3 related hwmon interfaces.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:18 -04:00
Evan Quan
cbf3f132fe drm/amd/powerplay: correct Navi1X temperature limit settings 
These are needed for temp1/2/3 related hwmon interfaces.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:09 -04:00
Evan Quan
0b590970a5 drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount 
The LCLK dpm table setup should be performed in .update_pcie_parameters().
Otherwise, the updated GenSpeed and LaneCount information will be lost.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:59 -04:00
Evan Quan
778f8e6afe drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting 
This can also help to maintain clear code layer.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:54 -04:00
Evan Quan
42f75c849f drm/amd/powerplay: drop unused APIs and parameters 
Leftover of previous performance level setting cleanups.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:48 -04:00
Evan Quan
982d68b093 drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2 
By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.

V2: fix compile warnings below
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds]
    freq = table->FClocks[dpm_level].Freq; \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
  GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
  ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds]
    freq = table->FClocks[dpm_level].Freq;  \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
  GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:38 -04:00
Evan Quan
d56ff01136 drm/amd/powerplay: drop unnecessary wrappers 
By calling the target APIs directly.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:32 -04:00
Evan Quan
5a7092ae56 drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs 
Before and after setting gfx clock soft max/min frequency.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:25 -04:00
Evan Quan
10e96d8973 drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range 
Use the common smu_v11_0_set_soft_freq_limited_range.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:19 -04:00
Evan Quan
b2785e250f drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs 
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:13 -04:00
Evan Quan
46a301e14e drm/amd/powerplay: drop unnecessary Navi1x specific APIs 
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:06 -04:00
Evan Quan
5a52694c75 drm/amd/powerplay: drop unnecessary Arcturus specific APIs 
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:00 -04:00
Evan Quan
768bb9010a drm/amd/powerplay: update the common API for performance level setting 
So that it can be more widely shared around SMU v11 ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:42:53 -04:00
Evan Quan
62cc9dd182 drm/amd/powerplay: update UMD pstate clock settings 
Preparing for coming code sharing around performance level
setting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:42:46 -04:00
Evan Quan
b64d86889f drm/amd/powerplay: add new UMD pstate data structure 
This is used to cache the clock frequencies for all UMD pstates.
So that we do not need to calculate from scratch on every UMD
pstate switch.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:42:40 -04:00