Commit Graph

948892 Commits

Author SHA1 Message Date
Jérôme Pouiller
a3d9682886 staging: wfx: remove useless defines
Several values defined in hif API are only here to define length of some
arrays. In most cases, they do not provide any extra information about
the size of the array (ie. "API_FIRMWARE_LABEL_SIZE" is only used to
define the size of member "firmware_label").

Remove these useless definitions.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Link: https://lore.kernel.org/r/20200406111756.154086-6-Jerome.Pouiller@silabs.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-13 14:32:36 +02:00
Jérôme Pouiller
29d69a59c4 staging: wfx: remove unused definitions from the hif API
Until now, hif API was directly imported from firmware sources.
However, it does not make sense to keep ton of unused structures in
the driver. Moreover, the hif API is now stable enough to be keep in
sync by importing delta from firmware.

So, drop unused definitions from the hif API.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Link: https://lore.kernel.org/r/20200406111756.154086-5-Jerome.Pouiller@silabs.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-13 14:32:36 +02:00
Jérôme Pouiller
a4aac6b889 staging: wfx: relocate TX_RETRY_POLICY_MAX and TX_RETRY_POLICY_INVALID to hif API
The definitions TX_RETRY_POLICY_MAX and TX_RETRY_POLICY_INVALID are
imposed by the hardware. Therefore, they should be located in the
hardware interface API.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Link: https://lore.kernel.org/r/20200406111756.154086-4-Jerome.Pouiller@silabs.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-13 14:32:35 +02:00
Jérôme Pouiller
d7dcf8a54e staging: wfx: relocate LINK_ID_NO_ASSOC and MAX_STA_IN_AP_MODE to hif API
The definitions LINK_ID_NO_ASSOC and MAX_STA_IN_AP_MODE are imposed by
the hardware. Therefore, they should be located in the hardware
interface API.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Link: https://lore.kernel.org/r/20200406111756.154086-3-Jerome.Pouiller@silabs.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-13 14:32:35 +02:00
Jérôme Pouiller
43aeff2c09 staging: wfx: drop unused WFX_LINK_ID_GC_TIMEOUT
The definition WFX_LINK_ID_GC_TIMEOUT is not used anymore since
commit d6aeba575f ("staging: wfx: simplify the link-id allocation")

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Link: https://lore.kernel.org/r/20200406111756.154086-2-Jerome.Pouiller@silabs.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-13 14:32:34 +02:00
Ryder Lee
1ba2ed7721 arm64: dts: mt7622: add built-in Wi-Fi device nodes
This enables built-in 802.11n Wi-Fi support. It's 2.4GHz only.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13 14:19:10 +02:00
Enric Balletbo i Serra
667c769246 soc / drm: mediatek: Fix mediatek-drm device probing
In the actual implementation the same compatible string
"mediatek,<chip>-mmsys" is used to bind the clock drivers
(drivers/soc/mediatek) as well as to the gpu driver
(drivers/gpu/drm/mediatek/mtk_drm_drv.c). This ends with the problem
that the only probed driver is the clock driver and there is no display
at all.

In any case having the same compatible string for two drivers is not
correct and should be fixed. To fix this, and maintain backward
compatibility, we can consider that the mmsys driver is the top-level
entry point for the multimedia subsystem, so is not a pure clock
controller but a system controller, and the drm driver is instantiated
by that MMSYS driver.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13 13:01:16 +02:00
Enric Balletbo i Serra
2c758e301e soc / drm: mediatek: Move routing control to mmsys device
Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
Those functions will allow DRM driver and others to control the data
path routing.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13 13:01:16 +02:00
Matthias Brugger
13032709e2 clk / soc: mediatek: Move mt8173 MMSYS to platform driver
There is no strong reason for this to use CLK_OF_DECLARE instead of
being a platform driver. Plus, MMSYS provides clocks but also a shared
register space for the mediatek-drm and the mediatek-mdp
driver. So move the MMSYS clocks to a new platform driver and also
create a new MMSYS platform driver in drivers/soc/mediatek that
instantiates the clock driver.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13 13:01:16 +02:00
Enric Balletbo i Serra
1a680aa888 dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller
The mmsys system controller is not only a pure clock controller, so
update the binding documentation to reflect that apart from providing
clocks, it also provides routing and miscellaneous control registers.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13 13:01:16 +02:00
Matthias Brugger
af19d64501 drm/mediatek: Omit warning on probe defers
It can happen that the mmsys clock drivers aren't probed before the
platform driver gets invoked. The platform driver used to print a warning
that the driver failed to get the clocks. Omit this error on
the defered probe path.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13 13:01:16 +02:00
Razvan Stefanescu
6a2ab88ca7 ARM: configs: at91: sama5: enable MCP16502 regulator
Driver is built as a module.

Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com>
Link: https://lore.kernel.org/r/20200325102223.24827-2-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:16 +02:00
Razvan Stefanescu
8d77c02961 ARM: configs: at91: sama5: enable SAMA5D2_PIOBU
Driver is enabled as a module.

Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com>
Link: https://lore.kernel.org/r/20200325102223.24827-1-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:16 +02:00
Ludovic Desroches
2fdc4e1c8c ARM: dts: at91: at91-sama5d27_som1: Enable eeprom device
There is an EEPROM on at91-sama5d27_som1 connected to i2c0. i2c0 node
has to be moved from at91-sama5d27_som1_ek to at91-sama5d27_som1.

Enable the i2c EEPROM found on at91-sama5d27_som1. Add an alias for the
i2c node.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200403061222.1277147-5-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:09 +02:00
Cyrille Pitchen
51cca920ce ARM: dts: at91: sama5d2_xplained: Add QSPI0 + SPI NOR memory nodes
This patch enables the QSPI0 controller, configures its pin muxing and
declares a jedec,spi-nor memory.

sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
memory which advertises a maximum frequency of 80MHz for Quad IO
Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200403061222.1277147-3-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:09 +02:00
Tudor Ambarus
0fd3a8f58f ARM: dts: at91: sam9x60ek: Add sdmmc1 node
sdmmc1 is not populated by default on sam9x60ek, but there are cases
where it is populated with wilc3000. Add the node, but keep it disabled.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200403061222.1277147-4-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:09 +02:00
Claudiu Beznea
471f0532ea ARM: dts: at91: sama5d27_som1: Add SPI NOR flash mapping
Add SoM1 flash mapping, identical with the other SPI NOR flash
mappings found on the other at91 boards.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200403061222.1277147-2-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:09 +02:00
Tudor Ambarus
c378150337 ARM: dts: at91: sam9x60ek: Use quad mode in the spi-nor flash
Both the QSPI controller and the sst26vf064b flash support
quad mode, enable it.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200403061222.1277147-1-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:09 +02:00
Ludovic Desroches
32542faf86 ARM: dts: at91: sama5d27_som1_ek: add an alias for i2c0
Add aliases for i2c devices to not rely on probe order for i2c device
numbering.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20200401221504.41196-5-ludovic.desroches@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Ludovic Desroches
d0815bc1b4 ARM: dts: at91: sama5d27_som1_ek: enable i2c0
Enable i2c0 controller.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20200401221504.41196-4-ludovic.desroches@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Ludovic Desroches
d08f4a5ac9 ARM: dts: at91: sama5d2_ptc_ek: add PB_USER as wakeup source
Add the push button PB_USER as wakeup source

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20200401221504.41196-3-ludovic.desroches@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Ludovic Desroches
baa998aecb ARM: dts: at91: sama5d2_ptc_ek: fix vbus pin
The gpio property for the vbus pin doesn't match the pinctrl and is
not correct.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Fixes: 42ed535595 "ARM: dts: at91: introduce the sama5d2 ptc ek board"
Cc: stable@vger.kernel.org # 4.19 and later
Link: https://lore.kernel.org/r/20200401221947.41502-1-ludovic.desroches@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Ludovic Desroches
a1af7f36c7 ARM: dts: at91: sama5d2_ptc_ek: fix sdmmc0 node description
Remove non-removable and mmc-ddr-1_8v properties from the sdmmc0
node which come probably from an unchecked copy/paste.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Fixes:42ed535595ec "ARM: dts: at91: introduce the sama5d2 ptc ek board"
Cc: stable@vger.kernel.org # 4.19 and later
Link: https://lore.kernel.org/r/20200401221504.41196-1-ludovic.desroches@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Alexandre Belloni
0e0e528d82 ARM: dts: at91: rm9200: switch to new clock bindings
Switch at91rm9200 boards to the new PMC clock bindings.

Link: https://lore.kernel.org/r/20200324124154.368335-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Alexandre Belloni
15090390ca ARM: dts: at91: at91sam9g45: switch to new clock bindings
Switch at91sam9g45 boards to the new PMC clock bindings.

Link: https://lore.kernel.org/r/20200117210619.17768-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Alexandre Belloni
82a5df83e4 ARM: dts: at91: at91sam9n12: switch to new clock bindings
Switch at91sam9n12 boards to the new PMC clock bindings.

Link: https://lore.kernel.org/r/20200116173510.427403-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Alexandre Belloni
7ed609b002 ARM: dts: at91: sama5d3: switch to new clock bindings
Switch sama5d3 boards to the new PMC clock bindings.

This prevents the wb50n to use the out of spec rate for USART1.

Link: https://lore.kernel.org/r/20200110222744.1261464-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-04-13 13:00:08 +02:00
Rajendra Nayak
aca48b61f9 opp: Manage empty OPP tables with clk handle
With OPP core now supporting DVFS for IO devices, we have instances of
IO devices (same IP block) which require an OPP on some platforms/SoCs
while just needing to scale the clock on some others.

In order to avoid conditional code in every driver which supports such
devices (to check for availability of OPPs and then deciding to do
either dev_pm_opp_set_rate() or clk_set_rate()) add support to manage
empty OPP tables with a clk handle.

This makes dev_pm_opp_set_rate() equivalent of a clk_set_rate() for
devices with just a clk and no OPPs specified, and makes
dev_pm_opp_set_rate(0) bail out without throwing an error.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2020-04-13 16:14:55 +05:30
Wolfram Sang
778627c78f ARM: s3c64xx: convert to use i2c_new_client_device()
Move away from the deprecated API and remove printing a stale 'ret'
value.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 12:28:23 +02:00
Marek Szyprowski
a836072787 ARM: exynos_defconfig: Compile MAC80211/CFG80211 as modules
MAC80211/CFG80211 framework requires loading regulatory.db from
/lib/firmware directory, so it makes very little sense to have it
built-in. Change it to be built as modules to let it properly load the
needed firmware/db files. As a side effect of this change, the size of
the compressed modules on SquashFS increased significantly from 27MiB
to 38MiB, so increase the size of BLK_DEV_RAM to allow the modules to
fit into it.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 12:22:04 +02:00
sachin agarwal
9b6d5690b5 gpio: ich: fix a typo
We had written "Mangagment" rather than "Management".

Signed-off-by: Sachin Agarwal <asachin591@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-04-13 13:18:18 +03:00
Andy Shevchenko
ccd025eadd pinctrl: baytrail: Enable pin configuration setting for GPIO chip
It appears that pin configuration for GPIO chip hasn't been enabled yet
due to absence of ->set_config() callback.

Enable it here for Intel Baytrail.

Fixes: c501d0b149 ("pinctrl: baytrail: Add pin control operations")
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-13 13:14:35 +03:00
Andy Shevchenko
5707dd73c7 pinctrl: cherryview: Use GENMASK() consistently
Use GENMASK() macro for all definitions where it's appropriate.
No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-13 13:14:35 +03:00
Andy Shevchenko
6b7275c877 pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H
It appears that SPT-H variant has different offset for PAD locking registers.
Fix it here.

Fixes: 551fa5801e ("pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-13 13:14:35 +03:00
Andy Shevchenko
36ad7b2448 pinctrl: cherryview: Re-use data structures from pinctrl-intel.h (part 2)
We have some data structures duplicated across the drivers.
Let's deduplicate them by using ones that being provided by
pinctrl-intel.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-13 13:14:35 +03:00
Jonathan Bakker
b577a27991 pinctrl: samsung: Correct setting of eint wakeup mask on s5pv210
Commit a8be2af021 ("pinctrl: samsung: Write external wakeup interrupt
mask") started writing the eint wakeup mask from the pinctrl driver.
Unfortunately, it made the assumption that the private retention data
was always a regmap while in the case of s5pv210 it is a raw pointer
to the clock base (as the eint wakeup mask not in the PMU as with newer
Exynos platforms).

Fixes: a8be2af021 ("pinctrl: samsung: Write external wakeup interrupt mask")
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 12:10:30 +02:00
Marek Szyprowski
f1b0ffaa68 ARM: dts: exynos: Enable WLAN support for the UniversalC210 board
Add a node for BCM4330/2 SDIO chip on SDHCI bus #3 and the required MMC
power sequence node for the Exynos4210-based UniversalC210 board.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
95384e977c ARM: dts: exynos: Enable WLAN support for the Rinato board
Add a node for BCM43342A SDIO chip on MSHC bus #1 and the required MMC
power sequence node for the Exynos3250-based Rinato board.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
d229280959 ARM: dts: exynos: Remove useless address/size cells for mshc_0 on Rinato
mshc_0 node doesn't have any children, so there is no need for address
and size-cells properties.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
ad0e74f0d6 ARM: dts: exynos: Correct the MAX8997 interrupts on the Trats board
Remove the 'interrupts' and 'interrupts-parent' properties, which have
been superseded by the interrupts-extended property. While touching this,
fix the interrupts flags to correctly describe the hardware.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
5453c5c9c5 ARM: dts: exynos: Correct regulator names
Both CPU-freq and dev-freq drivers support proper regulator lookup from
device-tree, so the early introduced hacks for registering main ARM VDD
regulator under 'vdd_arm' name are no longer needed. Similar for devfreq.
Fix this by removing the obsolete comments and changing the regulator
names to the one, which match the schematics and style for the given
board.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
8df80c1801 ARM: dts: exynos: Convert to new i2c-gpio bindings
The updated "i2c-gpio" driver bindings require to define the SDA and SCL
GPIO lines in the separate properties and mark both as GPIO_OPEN_DRAIN.
Covert all Exynos dts files to follow this style.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
8807d356bf ARM: dts: exynos: Fix GPIO polarity for thr GalaxyS3 CM36651 sensor's bus
GPIO lines for the CM36651 sensor I2C bus use the normal not the inverted
polarity. This bug has been there since adding the CM36651 sensor by
commit 85cb4e0bd2 ("ARM: dts: add cm36651 light/proximity sensor node
for exynos4412-trats2"), but went unnoticed because the "i2c-gpio"
driver ignored the GPIO polarity specified in the device-tree.

The recent conversion of "i2c-gpio" driver to the new, descriptor based
GPIO API, automatically made it the DT-specified polarity aware, what
broke the CM36651 sensor operation.

Fixes: 85cb4e0bd2 ("ARM: dts: add cm36651 light/proximity sensor node for exynos4412-trats2")
CC: stable@vger.kernel.org # 4.16+
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
a19f6efc01 ARM: dts: exynos: Enable WLAN support for the Trats board
Add a node for BCM4330/3 SDIO chip on SDHCI bus #3 and the required MMC
power sequence node for the Exynos4210-based Trats board.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Marek Szyprowski
b6353c31ab ARM: dts: exynos: Enable Bluetooth support for Rinato board
Add a node for the BCM43342A Bluetooth chip on the serial bus #0 on
the Exynos3250-based Rinato board.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Stenkin Evgeniy
8620cc2f99 ARM: dts: exynos: Add devicetree file for the Galaxy S2
Add devicetree file for the Exynos4210 based Galaxy S2 (GT-I9100
version).

Signed-off-by: Stenkin Evgeniy <stenkinevgeniy@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:36 +02:00
Paul Cercueil
15598aab6e dt-bindings: arm: samsung: Add compatible string for the Galaxy S2
Add compatible string for the Samsung Galaxy S2 (GT-I9100 version), which
is an Exynos4210 based device.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:42:31 +02:00
Marek Szyprowski
f8beebe019 ARM: exynos_defconfig: Enable serial bus and BCM HCIUART drivers
Enable serial bus and BCM HCIUART Bluetooth drivers available on the
Exynos3250-based Rinato board.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-13 11:40:34 +02:00
Borislav Petkov
2fa9a3cf30 x86/smpboot: Remove the last ICPU() macro
Now all is using the shiny new macros.

No code changed:

  # arch/x86/kernel/smpboot.o:

   text    data     bss     dec     hex filename
  16432    2649      40   19121    4ab1 smpboot.o.before
  16432    2649      40   19121    4ab1 smpboot.o.after

md5:
   a58104003b72c1de533095bc5a4c30a9  smpboot.o.before.asm
   a58104003b72c1de533095bc5a4c30a9  smpboot.o.after.asm

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20200324185836.GI22931@zn.tnic
2020-04-13 10:34:09 +02:00
Ingo Molnar
3b02a051d2 Merge tag 'v5.7-rc1' into locking/kcsan, to resolve conflicts and refresh
Resolve these conflicts:

	arch/x86/Kconfig
	arch/x86/kernel/Makefile

Do a minor "evil merge" to move the KCSAN entry up a bit by a few lines
in the Kconfig to reduce the probability of future conflicts.

Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-04-13 09:44:39 +02:00