In the refactoring of the coherency fabric assembly code, a function
called ll_get_cpuid() was created to factorize common logic between
functions adding CPU to the SMP coherency group, enabling and
disabling the coherency.
However, the name of the function is highly misleading: ll_get_cpuid()
makes one think tat it returns the ID of the CPU, i.e 0 for CPU0, 1
for CPU1, etc. In fact, this is not at all what this function returns:
it returns a CPU mask for the current CPU, usable for the coherency
fabric configuration and control registers.
Therefore this commit renames this function to
ll_get_coherency_cpumask(), and adds additional comments on top of the
function to explain in more details what it does, and also how the
endianess issue is handled.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-5-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Due a copy/paste error, the 'reg' values for the third PCIe interface
on Armada 380, and the third and fourth PCIe interfaces on Armada 385
are wrong: they are equal to the one of the second PCIe interface.
This patch fixes this by using the appropriate 'reg' values for those
PCIe interfaces.
Without this fix, the third and fourth PCIe interfaces are unusable on
those platforms.
Reported-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400597008-4148-1-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: 0d3d96ab00 ("ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs")
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
CPU core, the PL310 cache and the Marvell PCIe hardware block are
affected a L2/PCIe deadlock caused by a system erratum when hardware
I/O coherency is used.
This deadlock can be avoided by mapping the PCIe memory areas as
strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
removing the outer cache sync done in software. This is implemented in
this patch by:
* Registering a custom arch_ioremap_caller function that allows to
make sure PCI memory regions are mapped MT_UNCACHED.
* Adding at runtime the 'arm,io-coherent' property to the PL310 cache
controller. This cannot be done permanently in the DT, because the
hardware I/O coherency can only be enabled when CONFIG_SMP is
enabled, in the current kernel situation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400165974-9059-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Kconfig symbol USB_MUSB_PERIPHERAL was removed in v3.1. The last two
checks for its macro now always evaluate to false. So remove these
checks.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
[nsekhar@ti.com: also cleaned-up usage in defconfig file]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The i12 tvbox is an A20 based android tvbox, with 512M / 1G RAM, 4G nand flash,
ap6210 or ap6330 sdio wifi + bt (broadcom sdio wifi + uart attached brcm bt),
2USB host ports using USB-A receptacles and a micro-usb receptacle for USB OTG,
and 100Mbit ethernet using an IP101a phy.
The PCB is labelled i12-a20 hence I've named the board i12-a20. It is used
in noname allwinner A20 tv-boxes, which are sometimes sold with Q5 or
QT840A as product name.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
bus-width defaults to 1, and all 4 lines are hooked up at the cubietruck,
properly set bus-width to 4.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The following parameters are no longer needed by the edma driver since the
information can be obtained from the IP's CCCFG register:
n_channel, n_region, n_slot and n_tc.
Remove the initialization of n_cc as well since in this context it has no
meaning. We have separate edma_soc_info struct/eDMA3_CC instance so this
member does not make any sense (and the driver no longer uses it).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE
In case when booted with DT or the queue_priority_mapping is not provided
set up a default priority map.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
To be consistent in the code that we take parameters from edma_cc[j] struct
and not randomly from info[j] as well.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The struct edma is allocated per CC bases so the member num_cc does not make
any sense. One CC is one CC, it does not have sub CCs.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The Colombus has a full size SD slot wired to the MMC0 controller. In order to
work, the MMC lines have to have the pull-ups enabled though.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
The unit-address doesn't match the reg property. Since the reg property is
correct, change the unit-address accordingly.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The colombus board has a on-board USB hub, that is enabled through the pin
PH24, and wired to the first EHCI controller.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Meta idle function jumps into the interrupt handler which
efficiently blocks waiting for the next interrupt when it reads the
interrupt status register (TXSTATI). No other (polling) idle functions
can be used, therefore TIF_POLLING_NRFLAG is unnecessary, so lets remove
it.
Peter Zijlstra said:
> Most archs have (x86) hlt or (arm) wfi like idle instructions, and if
> that is your only possible idle function, you'll require the interrupt
> to wake up and there's really no point to having the POLLING bit.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/536CEB7E.9080007@imgtec.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Switch the device tree to the new compatibles introduced in the i2c drivers
to have a common pattern accross all Allwinner SoCs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
If CMA is turned on and CMA size is set to zero, kernel should
behave as if CMA was not enabled at compile time.
Every dma allocation should check existence of cma area
before requesting memory.
Signed-off-by: Gioh Kim <gioh.kim@lge.com>
Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Acked-by: Michal Nazarewicz <mina86@mina86.com>
[mszyprow: removed redundant empty line from the patch]
Signed-off-by: <m.szyprowski@samsung.com>
Samsung DT updates for v3.16
- exynos4
: add missing pinctrls
- exynos4412-trats2
: update camera nodes and add rear camera nodes
: rename alias for i2c_ak8975 label
Update camera nodes for exynos4 and exynos4412-trats2
- exynos5250
: update DWC3 usb controller and enable to use generic USB DRD phy
- exynos5250-snow
: enable dp-controller, fimd, hdmi and pwm backlight
: add sound node and Vbus regulator for USB 3.0
: add tps65090 power regulator
: add pinctrl for EC irq and i2c-arbitrator
- exynos5420
: change to correct compatible string for hdmi
: add PD entry to MFC codec and enable DWC3 and USB 3.0 PHY
: add MFC memory banks for smdk5420 and arndale-octa boards
- exynos5420-peach-pit
: add support exynos5420 based peach-pit board
: add sound node and Vbus regulatro for USB 3.0
: enable dp-controller, fimd
- exynos5420-smdk5420
: add Vbus regulatro for USB 3.0
- use generic DT bindings for map SYSRAM
[olof: Fixed up conflict with a fix for 4212 secondary CPU startup, carrying
over the fix to the reworked code]
* tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (32 commits)
ARM: dts: Add MFC memory banks to exynos5420 boards
ARM: dts: enable dp-controller for exynos5420-peach-pit board
ARM: dts: enable fimd for exynos5420 based peach-pit board
ARM: dts: enable dp-controller for exynos5250-snow board
ARM: dts: enable fimd for exynos5250-snow board
ARM: dts: enable pwm backlight for exynos5250-snow
ARM: dts: Add pwmX_out pinctrl nodes to exynos5250
ARM: dts: Add Vbus regulator for USB 3.0 on exynos5420-smdk5420
ARM: dts: Add Vbus regulator for USB 3.0 on exynos5420-peach-pit
ARM: dts: Add Vbus regulator for USB 3.0 on exynos5250-snow
ARM: dts: Add PD entry to MFC codec on exynos5420
ARM: dts: Add sound node for exynos5420-peach-pit board
ARM: dts: Add sound node for exynos5250-snow board
ARM: dts: Update DWC3 usb controller to use new phy driver for exynos5250
ARM: dts: Enable support for generic USB DRD phy for exynos5250
ARM: dts: Enable support for DWC3 controller for exynos5420
ARM: dts: Enable support for USB 3.0 PHY controller for exynos5420
ARM: dts: enable hdmi for exynos5420-peach-pit board
ARM: dts: change to correct compatible string for exynos5420 hdmi
ARM: dts: enable hdmi for exynos5250 based snow board
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Merging in Samsung fixes for 3.15-rc to avoid an annoying context conflict
with new DT code.
* commit '702b691e4a71':
ARM: dts: Remove g2d_pd node for exynos5420
ARM: dts: Remove mau_pd node for exynos5420
ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mount
ARM: dts: disable MDMA1 node for exynos5420
ARM: EXYNOS: fix the secondary CPU boot of exynos4212
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Samsung S3C24XX updates for 3.16" from Kukjin Kim:
Samsung S3C24XX to use the common clock framework
- S3C2412, S3C2413, S3C2416 and S3C2443 to use CCF
- S3C2410, S3C2440, S3C2442 to use CCF
- Remove legacy samsung clock from mach-s3c24xx/
- Some of them are missed from previous pull-request
- Clock related sutff got ack from Mike and Tomasz
- Created the last commit due to missing changes
during re-sorting because this branch is provided
as a base to samsung clk tree.
* tag 's3c24xx-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (23 commits)
ARM: S3C24XX: fix merge conflict
ARM: S3C24XX: remove SAMSUNG_CLOCK remnants after ccf conversion
ARM: S3C24XX: remove legacy clock code
ARM: S3C24XX: convert s3c2410 to common clock framework
ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock framework
ARM: S3C24XX: add platform code for conversion to the common clock framework
clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442
dt-bindings: add documentation for s3c2410 clock controller
ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled
clk: samsung: add clock driver for external clock outputs
ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccf
ARM: S3C24XX: convert s3c2412 to common clock framework
clk: samsung: add clock controller driver for s3c2412
dt-bindings: add documentation for s3c2412 clock controller
clk: samsung: add plls used by the early s3c24xx cpus
ARM: S3C24XX: only store clock registers when old clock code is active
ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
ARM: dts: add clock data for s3c2416
ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Pull "omap fixes for v3.15-rc cycle" from Tony Lindgren:
Regression fixes for omaps for NAND, DMA, cpu_idle and audio.
Also a minor one line fix for audio clock on 54xx.
* tag 'omap-for-v3.15/fixes-v3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4: Fix the boot regression with CPU_IDLE enabled
ARM: OMAP2+: Fix DMA hang after off-idle
ARM: OMAP2+: nand: Fix NAND on OMAP2 and OMAP3 boards
ARM: omap5: hwmod_data: Correct IDLEMODE for McPDM
ARM: OMAP3: clock: Back-propagate rate change from cam_mclk to dpll4_m5 on all OMAP3 platforms
Signed-off-by: Olof Johansson <olof@lixom.net>
It is ignored by the edma driver since we are just setting back the default
mapping of TC -> Queue.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
There is no need to change the default TC -> Queue mapping. By default the
mapping is: TC0 -> Q0, TC1 -> Q1, etc.
Changing this has no benefits at all and all the board files are just setting
the same mapping back to the HW.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Instead of saving the for loop length, take the num_tc value from the pdata.
In case of DT boot set the n_tc to 3 as it is hardwired in edma_of_parse_dt()
This is a temporary state since upcoming patch(es) will change how we are
dealing with these parameters.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The pdata has been just allocated with devm_kzalloc() in
edma_setup_info_from_dt() and passed to this function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Samsung fixes for 3.15 from Kukjin Kim:
- Remove g2d_pd and mau_pd nodes on exynos5420.
Since the power domains are linked to the CMU blocks,
kernel panic happens during access clocks when the
power domains are disabled. Now this is a best solution.
- Enable HS-I2C on exynos5 by default
MMC partition cannot be mounted for RFS without the
enabling HS-I2C because regulators for MMC power are
connected to HS-I2C bus.
- Disable MDMA1 node on exynos5420
When MDMA1 runs in secure mode it makes kernel fault,
so need to disalbe it on exynos5420 by default instead
of each board.
- Fix the secondary CPU boot for exynos4212
* tag 'samsung-fixes' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Remove g2d_pd node for exynos5420
ARM: dts: Remove mau_pd node for exynos5420
ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mount
ARM: dts: disable MDMA1 node for exynos5420
ARM: EXYNOS: fix the secondary CPU boot of exynos4212
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Second Round of Renesas ARM Based SoC r7s72100 CCF Updates for v3.16"
from Simon Horman:
r7s72100 (RZ/A1H) SoC based Genmai board
* Remove non-multiplatform support from genmai-reference
* tag 'renesas-r7s72100-ccf2-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Remove Genmai reference DTS
ARM: shmobile: Let Genmai multiplatform boot with Genmai DTB
ARM: shmobile: Sync Genmai DTS with Genmai reference DTS
ARM: shmobile: genmai-reference: Remove legacy clock support
ARM: shmobile: Remove non-multiplatform Genmai reference support
Signed-off-by: Olof Johansson <olof@lixom.net>
Get the two interrupt line number at the same time by merging the two
instance of if(node){}else{} places.
replace the &pdev->dev with the already existing dev which makes it possible
to collapse lines with devm_request_irq()
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge x86/espfix into x86/vdso, due to changes in the vdso setup code
that otherwise cause conflicts.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Add support to PHY of USB2 of the Exynos5250 SoC.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
[gautam.vivek@samsung.com: Split the usb phy entries]
[gautam.vivek@samsung.com: Added phy entry for OHCI also along with EHCI]
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds sysreg-syscon node to exynos5250 and exynos5420 device
tree, to access System Register's registers using syscon driver.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
[gautam.vivek@samsung.com: Split this syreg-syscon dts entry]
[gautam.vivek@samsung.com: added similar syscon entry for exynos5420]
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
[vikas.sajjan@samsung.com: updated the binding document]
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
DP Hpd Gpio pin which is "gpx2-6" in Exynos 5420 based peach board,
belongs to Pinctrl_0. It has moved to pinctrl_0 from pinctrl_3.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
