Add a new line to /proc/cpuinfo which shows all available facilities
as reported by the stfle instruction:
> cat /proc/cpuinfo
...
facilities : 0 1 2 3 4 6 7 ...
...
Reviewed-by: Peter Oberparleiter <oberpar@linux.vnet.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Commit af51160ebd ("s390/smp: initialize cpu_present_mask in
setup_arch") initializes the cpu_present_mask much earlier than
before. However the cpu detection code relies on the fact that iff
logical cpu 0 is marked present then also the corresponding physical
cpu address within the pcpu_devices array slot is valid.
Since commit 44fd22992c ("[PATCH] Register the boot-cpu in the cpu
maps earlier") this assumption is not true anymore. The patch marks
logical cpu 0 as present in common code without that architecture code
had a chance to setup the logical to physical map.
With that change the cpu detection code assumes that the physical cpu
address of cpu 0 is also 0, which is not necessarily true.
Subsequently the physical cpu address of the ipl cpu will be mapped to
a different logical cpu. If that cpu is brought online later the ipl
cpu will send itself an initial cpu reset sigp signal. This in turn
completely resets the ipl cpu and the system stops working.
A dump of such a system looks like a "store status" has been
forgotten. But actually the kernel itself removed all traces which
would allow to easily tell what went wrong.
To fix this initialize the logical to physical cpu address already in
smp_setup_processor_id(). In addition remove the initialization of the
cpu_present_mask and cpu_online_mask for cpu 0, since that has already
been done. Also add a sanity check, just in case common code will be
changed again...
The problem can be easily reproduced within a z/VM guest:
> chcpu -d 0
> vmcp ipl
Fixes: af51160ebd ("s390/smp: initialize cpu_present_mask in setup_arch")
Reported-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Reorder the operations in decompress_kernel() to ensure initrd is moved
to a safe location before the bss section is zeroed.
During decompression bss can overlap with the initrd and this can
corrupt the initrd contents depending on the size of the compressed
kernel (which affects where the initrd is placed by the bootloader) and
the size of the bss section of the decompressor.
Also use the correct initrd size when checking for overlaps with
parmblock.
Fixes: 06c0dd72ae ([S390] fix boot failures with compressed kernels)
Cc: stable@vger.kernel.org
Reviewed-by: Joy Latten <joy.latten@canonical.com>
Reviewed-by: Vineetha HariPai <vineetha.hari.pai@canonical.com>
Signed-off-by: Marcelo Henrique Cerri <marcelo.cerri@canonical.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
The OPP are declared as shared but no operating points are declared for
cpu1, 2 and 3. Thus, the following error happens during the boot:
cpu cpu1: dev_pm_opp_of_get_sharing_cpus: Couldn't find tcpu_dev node.
This patch applies the operating points to each cpu of the A33.
Fixes: 03749eb88e ("ARM: dts: sun8i: add opp-v2 table for A33")
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds a new system call to enable the use of guarded storage for
user space processes. The system call takes two arguments, a command
and pointer to a guarded storage control block:
s390_guarded_storage(int command, struct gs_cb *gs_cb);
The second argument is relevant only for the GS_SET_BC_CB command.
The commands in detail:
0 - GS_ENABLE
Enable the guarded storage facility for the current task. The
initial content of the guarded storage control block will be
all zeros. After the enablement the user space code can use
load-guarded-storage-controls instruction (LGSC) to load an
arbitrary control block. While a task is enabled the kernel
will save and restore the current content of the guarded
storage registers on context switch.
1 - GS_DISABLE
Disables the use of the guarded storage facility for the current
task. The kernel will cease to save and restore the content of
the guarded storage registers, the task specific content of
these registers is lost.
2 - GS_SET_BC_CB
Set a broadcast guarded storage control block. This is called
per thread and stores a specific guarded storage control block
in the task struct of the current task. This control block will
be used for the broadcast event GS_BROADCAST.
3 - GS_CLEAR_BC_CB
Clears the broadcast guarded storage control block. The guarded-
storage control block is removed from the task struct that was
established by GS_SET_BC_CB.
4 - GS_BROADCAST
Sends a broadcast to all thread siblings of the current task.
Every sibling that has established a broadcast guarded storage
control block will load this control block and will be enabled
for guarded storage. The broadcast guarded storage control block
is used up, a second broadcast without a refresh of the stored
control block with GS_SET_BC_CB will not have any effect.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Renesas ARM Based SoC DT Updates for v4.12
Cleanup:
* Drop superfluous status update for frequency override on various boards
* Always use status "okay" to enable devices on porger board
* Add INTC-SYS clock to device tree of various SoCs
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
* Remove unit-address and reg from integrated cache on various SoCs
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs
Enhancements:
* Add watchdog timer to r7s72100 SoC
* Update sdhi clock bindings on r7s72100 SoC
* tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
ARM: dts: silk: Drop superfluous status update for frequency override
ARM: dts: alt: Drop superfluous status update for frequency override
ARM: dts: gose: Drop superfluous status update for frequency override
ARM: dts: porter: Drop superfluous status update for frequency override
ARM: dts: koelsch: Drop superfluous status updates for frequency overrides
ARM: dts: lager: Drop superfluous status update for frequency override
ARM: dts: marzen: Drop superfluous status update for frequency override
ARM: dts: bockw: Drop superfluous status update for frequency override
ARM: dts: porter: Always use status "okay" to enable devices
ARM: dts: r8a7793: Add INTC-SYS clock to device tree
ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7794: Add INTC-SYS clock to device tree
ARM: dts: r8a7792: Add INTC-SYS clock to device tree
ARM: dts: r8a7791: Add INTC-SYS clock to device tree
ARM: dts: r8a7790: Add INTC-SYS clock to device tree
ARM: dts: r8a73a4: Add INTC-SYS clock to device tree
ARM: dts: r7s72100: Add watchdog timer
ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7794: Remove unit-address and reg from integrated cache
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Renesas ARM64 Based SoC DT Updates for v4.12
Cleanup:
* Drop superfluous status update for frequency override from all
r8a779[56] boards
* Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
* Remove unit-address and reg from integrated cache on r8a779[56] SoCs
Enhancements:
* Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
* Add Cortex-A53 CPU cores to r8a7795 SoC
* Update memory node to 4 GiB map on h3ulcb board
* Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
* Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
* Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
* Set drive-strength for ravb pins for r8a7795/salvator-x board
* Enable gigabit ethernet on r8a779[56]/salvator-x boards
* Enable I2C for DVFS device r8a779[56]/salvator-x boards
* tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits)
arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override
arm64: dts: m3ulcb: Drop superfluous status update for frequency override
arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides
arm64: dts: h3ulcb: Drop superfluous status update for frequency override
arm64: dts: r8a7796: Add Cortex-A53 PMU node
arm64: dts: r8a7796: Add Cortex-A53 CPU cores
arm64: dts: r8a7796: Add CA53 L2 cache-controller node
arm64: dts: r8a7796: Add Cortex-A57 PMU node
arm64: dts: r8a7796: Add Cortex-A57 CPU cores
arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC
arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins
arm64: dts: r8a7796: Remove unit-address and reg from integrated cache
arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches
arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support Suspend-to-RAM
arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM
arm64: dts: r8a7795: Add Cortex-A53 PMU node
arm64: dts: r8a7795: Add Cortex-A53 CPU cores
arm64: dts: r8a7796: Enable HSCIF DMA
arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1)
arm64: dts: r8a7796: Enable SCIF DMA
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Fixes for 4.11:
- Fix USB host for sama5d2
- Fix cpuidle on sama5
* tag 'at91-ab-4.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
ARM: at91: pm: cpu_idle: switch DDR to power-down mode
Revert "ARM: at91/dt: sama5d2: Use new compatible for ohci node"
Signed-off-by: Olof Johansson <olof@lixom.net>
Allwinner fixes for 4.11
A bunch of device tree fixes for various boards / SoCs.
* tag 'sunxi-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sun8i: a23/a33: drop bl_en_pin GPIO pinmux in reference design DTSI
ARM: dts: sun7i: lamobo-r1: Fix CPU port RGMII settings
ARM: sun8i: Fix the mali clock rate
Signed-off-by: Olof Johansson <olof@lixom.net>
i.MX fixes for 4.11:
- A fix to reboot hang seen on imx6sx-udoo-neo board, by removing
arm-supply and soc-supply and using LDO enabled mode.
* tag 'imx-fixes-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6sx-udoo-neo: Fix reboot hang
Signed-off-by: Olof Johansson <olof@lixom.net>
The moxart interrupt line flags were not respected in previous
driver: instead of assigning them per-consumer, a fixes mask
was set in the controller.
With the migration to a standard Faraday driver we need to
set up and handle the consumer flags correctly. Also remove
the Moxart-specific flags when switching to using real consumer
flags.
Extend the register window to 0x100 bytes as we may have a few
more registers in there and it doesn't hurt.
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Allow including of dtsi files in an architecture-independent manner.
Some dtsi files may be shared between architectures and one suggestion
was to have symlinks and let these includes get accessed via a
#include <arm64/foo.dtsi>
So add the necessary symlinks for arm32.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Allow including of dtsi files in an architecture-independent manner.
Some dtsi files may be shared between architectures and one suggestion
was to have symlinks and let these includes get accessed via a
#include <arm64/foo.dtsi>
So add the necessary symlinks for arm32.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
On VTLB+FTLB platforms (such as Loongson-3A R2), FTLB's pagesize is
usually configured the same as PAGE_SIZE. In such a case, Huge page
entry is not suitable to write in FTLB.
Unfortunately, when a huge page is created, its page table entries
haven't created immediately. Then the TLB refill handler will fetch an
invalid page table entry which has no "HUGE" bit, and this entry may be
written to FTLB. Since it is invalid, TLB load/store handler will then
use tlbwi to write the valid entry at the same place. However, the
valid entry is a huge page entry which isn't suitable for FTLB.
Our solution is to modify build_huge_handler_tail. Flush the invalid
old entry (whether it is in FTLB or VTLB, this is in order to reduce
branches) and use tlbwr to write the valid new entry.
Signed-off-by: Rui Wang <wangr@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15754/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Loongson-3's micro TLB (ITLB) is not strictly a subset of JTLB. That
means: when a JTLB entry is replaced by hardware, there may be an old
valid entry exists in ITLB. So, a TLB miss exception may occur while
handle_ri_rdhwr() is running because it try to access EPC's content.
However, handle_ri_rdhwr() doesn't clear EXL, which makes a TLB Refill
exception be treated as a TLB Invalid exception and tlbp may fail. In
this case, if FTLB (which is usually set-associative instead of set-
associative) is enabled, a tlbp failure will cause an invalid tlbwi,
which will hang the whole system.
This patch rename handle_ri_rdhwr_vivt to handle_ri_rdhwr_tlbp and use
it for Loongson-3. It try to solve the same problem described as below,
but more straightforwards.
https://patchwork.linux-mips.org/patch/12591/
I think Loongson-2 has the same problem, but it has no FTLB, so we just
keep it as is.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Rui Wang <wangr@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15753/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The vpe_mask member of struct core_boot_config is of type atomic_t,
which is a 32bit type. In cps-vec.S this member was being retrieved by a
PTR_L macro, which on 64bit systems is a 64bit load. On little endian
systems this is OK, since the double word that is retrieved will have
the required less significant word in the correct position. However, on
big endian systems the less significant word of the load is retrieved
from address+4, and the more significant from address+0. The destination
register therefore ends up with the required word in the more
significant word
e.g. when starting the second VP of a big endian 64bit system, the load
PTR_L ta2, COREBOOTCFG_VPEMASK(a0)
ends up setting register ta2 to 0x0000000300000000
When this value is written to the CPC it is ignored, since it is
invalid to write anything larger than 4 bits. This results in any VP
other than VP0 in a core failing to start in 64bit big endian systems.
Change the load to a 32bit load word instruction to fix the bug.
Fixes: f12401d721 ("MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes")
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15787/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Hook up three pkey syscalls (which we don't implement) and the new statx
syscall, as has been done for arch/arm/.
Signed-off-by: Will Deacon <will.deacon@arm.com>
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Enable drivers specific to Exynos5433 and Exynos7:
1. MFD Low Power Audio SubSystem (LPASS),
2. DRM drivers (DECON display, outputs),
3. Drivers for video-related sub-blocks (JPEG, Multi Format Codec,
GScaler).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Enable EXYNOS_PM_DOMAINS because recently Exynos5433 got support for
Power Management domains. The Exynos5433 pinctrl driver requires
EXYNOS_PMU to get the syscon-regmap for PMU address space.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
kprobes test cases need to have a stack that is aligned to an 8-byte
boundary because they call other functions (and the ARM ABI mandates
that alignment) and because test cases include 64-bit accesses to the
stack. Unfortunately, GCC doesn't ensure this alignment for inline
assembler and for the code in question seems to always misalign it by
pushing just the LR register onto the stack. We therefore need to
explicitly perform stack alignment at the start of each test case.
Without this fix, some test cases will generate alignment faults on
systems where alignment is enforced. Even if the kernel is configured to
handle these faults in software, triggering them is ugly. It also
exposes limitations in the fault handling code which doesn't cope with
writes to the stack. E.g. when handling this instruction
strd r6, [sp, #-64]!
the fault handling code will write to a stack location below the SP
value at the point the fault occurred, which coincides with where the
exception handler has pushed the saved register context. This results in
corruption of those registers.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Kprobes/arm skips single-stepping (moreover handling the event)
if the conditional instruction must not be executed. This
also apply the rule when we hit the recursing kprobe, so
that kprobe does not count nmissed up in that case.
Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
This is arm port of commit 6a5022a56a ("kprobes/x86: Allow to
handle reentered kprobe on single-stepping")
Since the FIQ handlers can interrupt in the single stepping
(or preparing the single stepping, do_debug etc.), we should
consider a kprobe is hit in the NMI handler. Even in that
case, the kprobe is allowed to be reentered as same as the
kprobes hit in kprobe handlers
(KPROBE_HIT_ACTIVE or KPROBE_HIT_SSDONE).
The real issue will happen when a kprobe hit while another
reentered kprobe is processing (KPROBE_REENTER), because
we already consumed a saved-area for the previous kprobe.
Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
The highest supported frequency (1.2GHz) requires to "overvolt" the CPU.
However, some boards still do not have the cpu-supply DT property in the
cpu DT node which means that the CPU will always run with the same input
voltage but try to run at 1.2GHz frequency. This is the source of
(experienced) CPU crashes.
Remove the OPP which requires overvolting the CPU until all boards have
a cpu-supply property.
Fixes: 03749eb88e ("ARM: dts: sun8i: add opp-v2 table for A33")
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The digital AIF interfaces has been renamed in the sun8i audio codec
driver so the audio-routing in the device tree must be renamed too.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
XHCI debug capability (DbC) is an optional but standalone
functionality provided by an xHCI host controller. Software
learns this capability by walking through the extended
capability list of the host. XHCI specification describes
DbC in section 7.6.
This patch introduces the code to probe and initialize the
debug capability hardware during early boot. With hardware
initialized, the debug target (system on which this code is
running) will present a debug device through the debug port
(normally the first USB3 port). The debug device is fully
compliant with the USB framework and provides the equivalent
of a very high performance (USB3) full-duplex serial link
between the debug host and target. The DbC functionality is
independent of the xHCI host. There isn't any precondition
from the xHCI host side for the DbC to work.
One use for this feature is kernel debugging, for example
when your machine crashes very early before the regular
console code is initialized. Other uses include simpler,
lockless logging instead of a full-blown printk console
driver and klogd.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mathias Nyman <mathias.nyman@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-usb@vger.kernel.org
Link: http://lkml.kernel.org/r/1490083293-3792-3-git-send-email-baolu.lu@linux.intel.com
[ Small fix to the Kconfig help text. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
POWER8 uses bit 36 in SRR1 like POWER9 for i-side machine checks, and
contains several conditions for link timeouts that are not currently
handled.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Move the handling (corrective action) of machine checks to the table
based evaluation.
This changes P7 and P8 ERAT flushing from using SLB flush to using ERAT
flush.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Have machine types define i-side and d-side tables to describe their
machine check encodings, and match entries to evaluate (for reporting)
machine checks.
Functionality is mostly unchanged (tested with a userspace harness), but
it does make a change in that it no longer records DAR as the effective
address for those errors where it is specified to be invalid (which is a
reporting change only).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Use the flush function introduced with the POWER9 machine check handler
for POWER7 and 8, rather than open coding it multiple times in callers.
There is a specific ERAT flush type introduced for POWER9, but the
POWER7-8 ERAT errors continue to do SLB flushing (which also flushes
ERAT), so as not to introduce functional changes with this cleanup
patch.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Print the faulting address of the machine check that may help with
debugging. The effective address reported can be a target memory address
rather than the faulting instruction address.
Fix up a dangling bracket while here.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The symbols exported for use by MOL/rtlinux aren't getting CRCs and I
was about to fix that. But MOL is dead upstream, and the latest work on
it was to make it use KVM instead of its own kernel module. So remove
them instead.
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Since the fault retry is now handled earlier, we can release the
mmap_sem lock earlier too and remove later unlocking previously done in
mm_fault_error().
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
In do_page_fault() if handle_mm_fault() returns VM_FAULT_RETRY, retry
the page fault handling before anything else.
This would simplify the handling of the mmap_sem lock in this part of
the code.
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
