Commit Graph

38348 Commits

Author SHA1 Message Date
Thomas Hellstrom
3ce7803cf3 drm/ttm: Avoid calling drm_ht_remove from atomic context
On recent kernels, calling drm_ht_remove triggers a might_sleep() warning
from within vfree(). So avoid calling it from atomic context. The use-cases
we fix here are both from destructors so there should be no concurrent
use of the hash tables.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2017-03-30 11:43:40 +02:00
Thomas Hellstrom
fe25deb773 drm/ttm, drm/vmwgfx: Relax permission checking when opening surfaces
Previously, when a surface was opened using a legacy (non prime) handle,
it was verified to have been created by a client in the same master realm.
Relax this so that opening is also allowed recursively if the client
already has the surface open.

This works around a regression in svga mesa where opening of a shared
surface is used recursively to obtain surface information.

Cc: <stable@vger.kernel.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2017-03-30 11:43:39 +02:00
Murray McAllister
63774069d9 drm/vmwgfx: avoid calling vzalloc with a 0 size in vmw_get_cap_3d_ioctl()
In vmw_get_cap_3d_ioctl(), a user can supply 0 for a size that is
used in vzalloc(). This eventually calls dump_stack() (in warn_alloc()),
which can leak useful addresses to dmesg.

Add check to avoid a size of 0.

Cc: <stable@vger.kernel.org>
Signed-off-by: Murray McAllister <murray.mcallister@insomniasec.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2017-03-30 11:43:37 +02:00
Murray McAllister
36274ab8c5 drm/vmwgfx: NULL pointer dereference in vmw_surface_define_ioctl()
Before memory allocations vmw_surface_define_ioctl() checks the
upper-bounds of a user-supplied size, but does not check if the
supplied size is 0.

Add check to avoid NULL pointer dereferences.

Cc: <stable@vger.kernel.org>
Signed-off-by: Murray McAllister <murray.mcallister@insomniasec.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2017-03-30 11:43:23 +02:00
Thomas Hellstrom
f7652afa8e drm/vmwgfx: Type-check lookups of fence objects
A malicious caller could otherwise hand over handles to other objects
causing all sorts of interesting problems.

Testing done: Ran a Fedora 25 desktop using both Xorg and
gnome-shell/Wayland.

Cc: <stable@vger.kernel.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2017-03-30 11:42:54 +02:00
Christopher Spinrath
f56c9202b5 drm/bridge: ti-tfp410: support hpd via gpio
On some boards the hpd pin of a hdmi connector is wired up to a gpio
pin. Since in the DRM world the tfp410 driver is responsible for
handling the connector, add support for hpd gpios in this very driver.

Reviewed-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/2e47786ab3d04078ae70d0c4064f7c4d@rwthex-s1-b.rwth-ad.de
2017-03-30 15:06:47 +05:30
Maarten Lankhorst
a2e1319d1f Revert unrelated part of "drm: simplify the locking in the GETCRTC ioctl"
v2 of the commit 2c77bb29d3 ("drm: simplify the locking in the GETCRTC ioctl")
accidentally introduced a unrelated change in intel_display.c, revert the
unrelated change.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Fixes: 2c77bb29d3 ("drm: simplify the locking in the GETCRTC ioctl")
Reported-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/6be47261-475f-c190-af56-c136677246d9@linux.intel.com
2017-03-30 09:55:46 +02:00
Daniel Vetter
1fa4da043a drm: Fixup failure paths in drm_atomic_helper_set_config
I've screwed this up when removing the legacy backoff hack.

Fixes: 38b6441e4e ("drm/atomic-helper: Remove the backoff hack from set_config")
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20170329174136.10330-1-daniel.vetter@ffwll.ch
2017-03-30 09:36:29 +02:00
Jani Nikula
2e5fec5f62 drm/i915/opregion: debug log about invalid ACPI OpRegion VBT
Leave more breadcrumbs for debuggers.

Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1490783578-6065-3-git-send-email-jani.nikula@intel.com
2017-03-30 09:12:36 +03:00
Jani Nikula
ccbf6b6498 drm/i915/opregion: try to validate RVDA VBT only if it's there
Seems more sensible this way, and reduces indent for the more common
case.

Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1490783578-6065-2-git-send-email-jani.nikula@intel.com
2017-03-30 09:11:34 +03:00
Jani Nikula
0e53f472c3 drm/i915/opregion: bail out early for systems with no opregion VBT
Reduce indent. No functional changes.

Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1490783578-6065-1-git-send-email-jani.nikula@intel.com
2017-03-30 09:06:52 +03:00
Zhi Wang
b79c52aef3 drm/i915/gvt: Activate/de-activate vGPU in mdev ops.
This patch introduces two functions for activating/de-activating vGPU in
mdev ops.

A racing condition was found between virtual vblank emulation and KVGMT
mdev release path. V-blank emulation will emulate and inject V-blank
interrupt for every active vGPU with holding gvt->lock, while in mdev
release path, it will directly release hypervisor handle without changing
vGPU status or taking gvt->lock, so a kernel oops is encountered when
vblank emulation is injecting a interrupt with a invalid hypervisor
handle. (Reported by Terrence)

To solve this problem, we factor out vGPU activation/de-activation from
vGPU creation/destruction path and let KVMGT mdev release ops de-activate
the vGPU before release hypervisor handle. Once a vGPU is de-activated,
GVT-g will not emulate v-blank for it or touch the hypervisor handle.

Fixes: 659643f ("drm/i915/gvt/kvmgt: add vfio/mdev support to KVMGT")
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:37:53 +08:00
Ping Gao
b35f34d1da drm/i915/gvt: control the scheduler by timeslice usage
The timeslice usage will determine vGPU whether has chance to
schedule or not at every vGPU switch checkpoint.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:34:10 +08:00
Ping Gao
afe04fbe6c drm/i915/gvt: create an idle vGPU
vGPU resource is allocated by scheduler. To account for non-allocated
free cycles, we create an idle vGPU as the placeholder similar to idle task
concept, which is useful to handle some corner cases in scheduling policy.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:34:07 +08:00
Ping Gao
39d467c2b7 drm/i915/gvt: add basic function for weight control
This method tries to guarantee precision in second level, with the
adjustment conducted in every 100ms. At the end of each vGPU switch
calculate the sched time and subtract it from the time slice
allocated; the allocated time slice for every 100ms together with
remaining timeslice, will be used to decide how much timeslice
allocated to this vGPU in the next 100ms slice, with the end goal
to guarantee weight ratio in second level.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:34:04 +08:00
Ping Gao
bc90d097ae drm/i915/gvt: define weight according to vGPU type
The weight defines proportional control of physical GPU resource
shared between vGPUs. So far the weight is tied to a specific vGPU
type, i.e when creating multiple vGPUs with different types, they
will inherit different weights.

e.g. The weight of type GVTg_V5_2 is 8, the weight of type GVTg_V5_4
is 4, so vGPU of type GVTg_V5_2 has double vGPU resource of vGPU type
GVTg_V5_4.

TODO: allow user control the weight setting in the future.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:33:58 +08:00
Ping Gao
32356920da drm/i915/gvt: factor out the scheduler
Factor out the scheduler to a more clear structure, the basic
logic is to find out next vGPU first and then schedule it.
vGPUs were ordered in a LRU list, scheduler scan from the LRU
list head and choose the first vGPU who has pending workload.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:32:31 +08:00
Ping Gao
f6504cce54 drm/i915/gvt: add some statistic routine for scheduler
Add some statistic routine to collect the time when vGPU is
scheduled in/out and the time of the last ctx submission.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:32:28 +08:00
Ping Gao
91d0101ad3 drm/i915/gvt: use hrtimer replace delayed_work in scheduler
Currently the scheduler is triggered by delayed_work, which doesn't
provide precision at microsecond level. Move to hrtimer instead for
more accurate control.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:32:24 +08:00
Tina Zhang
865f03d42e drm/i915/gvt: remove the redundant info NULL check
The variable info is never NULL, which is checked by the caller. This
patch removes the redundant info NULL check logic.

Fixes: 695fbc08d8 ("drm/i915/gvt: replace the gvt_err with gvt_vgpu_err")
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:32:12 +08:00
Zhenyu Wang
bf39ec335e drm/i915/gvt: adjust mem size for low resolution type
From commit d1a513be1f ("drm/i915/gvt: add resolution definition for vGPU
type"), small type has been restricted to small resolution, so not
require larger high GM size any more. Change to smaller 384M for more
VM creation with vGPU enabled which still perform reasonable workload.

Fixes: d1a513be1f ("drm/i915/gvt: add resolution definition for vGPU type")
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 13:32:02 +08:00
Xiangliang Yu
c6f3e7cb13 drm/amdgpu/soc15: enable psp block for SRIOV
SRIOV can support for loading ucode with PSP block, enable it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:55 -04:00
Xiangliang Yu
cfd8373320 drm/amdgpu/soc15: bypass pp block for vf
Disable pp block if device is  vf.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:55 -04:00
Xiangliang Yu
6668b73446 drm/amdgpu/psp: add check sOS sign
Confirm if sys driver and sOS are already been loaded through sOS
sign register, skip loading sys driver and sOS if finding the sign.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:54 -04:00
Tom St Denis
ec63982e90 drm/amd/amdgpu: Correct ring wptr address in debugfs (v2)
On gfx9 hardware the value is not wrapped and is a 64-bit value.  So
we reduce it modulo the ring size.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

(v2) use buf_mask instead of computing on the fly

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:53 -04:00
Felix Kuehling
1866bac897 drm/amdgpu: Fix multi-level page table bugs for large BOs v3
Fix the start/end address calculation for address ranges that span
multiple page directories in amdgpu_vm_alloc_levels.

Add error messages if page tables aren't found. Otherwise the page
table update would just fail silently.

v2:
 * Change WARN_ON to WARN_ON_ONCE
 * Move masking of high address bits to caller
 * Add range-check for "from" and "to"
v3:
 * Replace WARN_ON_ONCE in get_pt with pr_err in caller

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:53 -04:00
Felix Kuehling
9ceaeeafbd drm/amdgpu: Fix Vega10 VM initialization
adev->family is not initialized yet when amdgpu_get_block_size is
called. Use adev->asic_type instead.

Minimum VM size is 512GB, not 256GB, for a single page table entry
in the root page table.

gmc_v9_0_vm_init is called after adev->vm_manager.max_pfn is
initialized. Move the minimum VM-size enforcement ahead of max_pfn
initializtion. Cast to 64-bit before the left-shift.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:52 -04:00
Felix Kuehling
22770e5a75 drm/amdgpu: Make max_pfn 64-bit
With 4-level page tables the maximum VM size is 256TB. That's 64G
pages, which can't be represented in 32-bit.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:51 -04:00
Christian König
43e669d65e drm/amdgpu: drop GB_GPU_ID from the golden settings
That register is marked deprecated, reading it results in a bus error.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:51 -04:00
Junwei Zhang
b9be700e38 drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v3)
v2: fix for all sdma engines
v3: squash in fix for SI/CI

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:50 -04:00
Jim Qu
bd7d7acf55 drm/amd/amdgpu: fix Tonga S3 resume hang on rhel6.8
1. security firmware loading has moved to sw init, so this code
   is useless.
2. it seems that driver could not call request_firmware on
   kernel 2.6, when S3 resume. for request firmware depends on
   userspace, at this time, userspace is freeze.

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:49 -04:00
Roger.He
c309cd03b4 drm/amd/amdgpu: fix performance drop when VRAM pressure
When VRAM pressue and trigger huge evictions there is performance drop,
this patch fix it.

Signed-off-by: Roger.He <Hongbo.He@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:48 -04:00
Harry Wentland
e51a3226d4 drm/amdgpu: Couple small warning fixes
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:48 -04:00
Felix Kuehling
4d6cbde37a drm/amdgpu: Clean up GFX 9 VM fault messages
Clean up the VM fault message format and use rate-limiting similar
to other ASICs.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:47 -04:00
Felix Kuehling
d7c434d367 drm/amdgpu: Register UTCL2 as a source of VM faults
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:46 -04:00
Alex Deucher
480e9150ea drm/amdgpu/soc15: drop support for reading some registers
The RB harvest registers are not necessary, the driver already
exposes this info via the info ioctl.  GB_BACKEND_MAP has
been deprecated since SI and is not relevant to the RB mapping.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:46 -04:00
Alex Deucher
c013cea2df drm/amdgpu/soc15: return cached values for some registers (v2)
Required for SR-IOV and saves MMIO transactions.

v2: drop cached RB harvest registers

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:45 -04:00
Alex Deucher
2572c24ca9 drm/amdgpu/gfx9: use hweight for calculating num_rbs
Match what we do for other asics.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:44 -04:00
Alex Deucher
f2713e8c2a drm/amdgpu: refine the logic in amdgpu_need_post()
We check the mem config register to make sure it's been
programmed by the vbios to determine if we need to post
so we check for a non-0 value.  However, when the asic
comes out of reset, we may see all ones here, so check
for that too.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:44 -04:00
Andrey Grodzovsky
e5f586c763 drm/amdgpu: Add interrupt entries for CRTC_VERTICAL_INTERRUPT0.
This used by DAL ISR logic for VBLANK handling.

Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:43 -04:00
Monk Liu
e9d672b291 drm/amdgpu:changes in gfx DMAframe scheme (v2)
1) Adapt to vulkan:
Now use double SWITCH BUFFER to replace the 128 nops w/a,
because when vulkan introduced, umd can insert 7 ~ 16 IBs
per submit which makes 256 DW size cannot hold the whole
DMAframe (if we still insert those 128 nops), CP team suggests
use double SWITCH_BUFFERs, instead of tricky 128 NOPs w/a.

2) To fix the CE VM fault issue when MCBP introduced:
Need one more COND_EXEC wrapping IB part (original one us
for VM switch part).

this change can fix vm fault issue caused by below scenario
without this change:

>CE passed original COND_EXEC (no MCBP issued this moment),
 proceed as normal.

>DE catch up to this COND_EXEC, but this time MCBP issued,
 thus DE treats all following packages as NOP. The following
 VM switch packages now looks just as NOP to DE, so DE
 dosen't do VM flush at all.

>Now CE proceeds to the first IBc, and triggers VM fault,
 because DE didn't do VM flush for this DMAframe.

3) change estimated alloc size for gfx9.
with new DMAframe scheme, we need modify emit_frame_size
for gfx9

4) No need to insert 128 nops after gfx8 vm flush anymore
because there was double SWITCH_BUFFER append to vm flush,
and for gfx7 we already use double SWITCH_BUFFER following
after vm_flush so no change needed for it.

5) Change emit_frame_size for gfx8

v2: squash in BUG removal from Monk

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:42 -04:00
Monk Liu
eeb2487df7 drm/amdgpu:fix missing programing critical registers
those MC_VM registers won't be programed by VBIOS in VF
so driver is responsible to programe them.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:42 -04:00
Monk Liu
5846e35569 drm/amdgpu:fix ring_write_multiple
ring_write_multiple should use buf_mask instead of ptr_mask

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:41 -04:00
Monk Liu
79a0c4655e drm/amdgpu:fix gmc_v9 vm fault process for SRIOV
for SRIOV we cannot use access register when in IRQ routine
with regular KIQ method

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:41 -04:00
Monk Liu
6e9dc86121 drm/amdgpu:no cg for soc15 of SRIOV
no CG for SRIOV on SOC15

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:40 -04:00
Monk Liu
32833fb732 drm/amdgpu:two fixings for sdma v4 for SRIOV
no hw_fini for SRIOV, otherwise other VF will be affected
no CG for SRIOV

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:39 -04:00
Monk Liu
ca82a746b0 drm/amdgpu:change sequence of SDMA v4 init
must set minor_update.enable before write smaller value
to wptr/doorbell, so for sriov we need set that register
bit in hw_init period.

this could fix the SDMA ring test fail after guest reboot

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:39 -04:00
Monk Liu
e09706f46e drm/amdgpu:fix ring init sequence
ring->buf_mask need be set prior to ring_clear_ring invoke
and fix ring_clear_ring as well which should use buf_mask
instead of ptr_mask

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:38 -04:00
Monk Liu
b4d6126d1e drm/amdgpu:virt_init_setting invoke is missed!
this must be invoked during early init

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:37 -04:00
Monk Liu
2e2e3c7f18 drm/amdgpu:enable MCBP for SR-IOV (v2)
Apply the new IB during IB emit for SRIOV with MCBP

v2: agd: use define instead of magic number

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:36 -04:00