Correct the invalid clock for the sgtl5000 audio codec on the GW52xx Ventana
baseboard.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The vendor prefix for Linear Technology should be lltc,
same as the NASDAQ symbol.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
imx6sl fec MDIO clock source is from ipg 66Mhz, but the currect imx6sl
device tree define it as "enet_ref" clock (50Mhz), so the patch just
corrects imx6sl dtsi fec "ipg" clock.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds a default PCIe bus clock node.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[horms+renesas@verge.net.au: resolved conflict]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Henninger board dependent part of the I2C2 device node.
Based on the Koelsch I2C2 device tree patch by Wolfram Sang.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
A second i2c6 node was a added by
05e234a187058ee ("ARM: shmobile: koelsch dts: Add VDD MPU regulator for
DVFS"). Merge this into the existing node.
Also shuffle i2c nodes so they are all together.
Cc: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Due to an error when merging df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") a duplicate i2c3 node.
This patch moves the duplicate and moves to old node to
be closer to the other new i2c nodes.
Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the Lager DTS to make use of the new unified legacy
memory map where the legacy window on Lager and Koelsch
have the same size.
With this change in place the code gets aligned with the
documentation.
After update the Lager board has the following map:
Bank0: 1GiB RAM (Legacy 32-bit: 0x40000000->0x7fffffff)
Bank1: 3GiB RAM (LPAE area: 0x140000000->0x1ffffffff)
Before the update the old map looked like this:
Bank0: 2GiB RAM (Legacy 32-bit: 0x40000000->0xbfffffff)
Bank1: 2GiB RAM (LPAE area: 0x180000000->0x1ffffffff)
Tested with and without LPAE on r8a7790 Lager.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Due to an error when resolving conflicts df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") added the i2c[12]_pins nodes to the wrong
node.
This patch moves them to their correct location in the pfc node.
Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add pinctrl definitions for i2c1 and i2c2 busses on the Lager board
to ensure these are setup correctly at initialisation time. The i2c0
and i2c3 busses are connected to single function pins.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to patch title]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add i2c0, i2c1, i2c2 and i2c3 nodes to the Lager reference device tree as
these busses all have devices on them that can be probed even if they
are no drivers yet.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to title]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.
- voltage-tolerance = 1%
It reflects the tolerance for the CPU voltage defined inside the OPP
table. Due to the lack of proper OPP definition, use an arbitrary safe
value.
- clock-latency = 300 us
Approximate worst-case latency to do a full DVFS transition for every
OPPs. Due to the lack of HW information, use an arbitrary safe value.
Note: The term transition-latency will be more accurate to define this
value since the clock transition latency is not the only parameter that
will define the overall DVFS transition.
- operating-points = < kHz - uV >
List of 6 operating points. All of them are using the same voltage
since DVS is not supported in R-CAR Gen2.
- clocks
phandle to the CPU clock source. This clock source is used for all the
2 CortexA15 located inside the same cluster.
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The CA15 cluster is capable of voltage scaling. Add the regulator
in the i2c6 node, to allow the generic CPUFreq driver to use it.
Enable the i2c6 pin mux and the device node as well since the
da9210 is connected to that bus.
Note: In R-CAR Gen2, each frequency is using the same voltage,
and DVS control is not used. Therefore, this patch set the
voltage(Vmin/Vmax) to 1000mv.
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.
- voltage-tolerance = 1%
It reflects the tolerance for the CPU voltage defined inside the OPP
table. Due to the lack of proper OPP definition, use an arbitrary safe
value.
- clock-latency = 300 us
Approximate worst-case latency to do a full DVFS transition for every
OPPs. Due to the lack of HW information, use an arbitrary safe value.
Note: The term transition-latency will be more accurate to define this
value since the clock transition latency is not the only parameter that
will define the overall DVFS transition.
- operating-points = < kHz - uV >
List of 6 operating points. All of them are using the same voltage
since the valid Vmin voltage is not documented in the HW spec.
- clocks
phandle to the CPU clock source. This clock source is used for all the
4 CortexA15 located inside the same cluster.
Signed-off-by: Benoit Cousson <bcousson+renesas@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0]
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The CA15 cluster is capable of voltage scaling. Add the regulator
in the i2c3 node, to allow the generic CPUFreq driver to use it.
Enable the i2c3 pin mux and the device node as well since the
da9210 is connected to that bus.
Note: In R-CAR Gen2, each frequency is using the same voltage,
and DVS control is not used. Therefore, this patch set the
voltage(Vmin/Vmax) to 1000mv.
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Changes Vmin for disabling DVS]
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that SCIF devices are initialised using DT it should
not be necessary to use the work around to provide clocks any more.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
As early printk support is not enabled in the kernel in the
shmobile defconfig it does not make much sense to provide for
it in the default command line.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Warning (ranges_format): /clocks has empty "ranges" property but its #address-cells (2) differs from / (1)
Warning (ranges_format): /clocks has empty "ranges" property but its #size-cells (2) differs from / (1)
As r8a7779 doesn't support LPAE, change #address-cells and #size-cells from
"<2>" to "<1>", and update the affected "reg" properties to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- Correct the unit-address for the "cpg_clocks" node,
- Add missing unit-addresses for the "mstp*_clks" nodes,
- Rename "cpg_clocks" and "mstp*_clks" nodes to the more generic
"clocks".
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Convert the Marzen DT reference board support to use shmobile_init_delay()
to be able to migrate away from per-SoC delay setup functions.
Based on work for the Armadillo800 EVA board by Magnus Damm.
Cc: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Convert the common C-code-less r8a7779 DT board support
to use shmobile_init_delay() to be able to migrate away
from per-SoC delay setup functions.
Based on work by Magnus dam for the r8a7740 SoC.
Cc: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add 1GHz to the r8a7779 DTS to describe the maximum CPU frequency.
Based on work by Magnus dam for the r8a7740 SoC.
Cc: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Marzen DT reference is now only built for multiplatform
which means that CCF comes with the package. Remove unused legacy
code ifdefs to clean up the code.
Based on similar work for the Koelsch board by Magnus Damm.
Cc: Magnus Damm <damm@opensource.se>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that the DTS file r8a7779-marzen.dts can be used with
board-marzen.c and board-marzen-reference.c, proceed with removing
r8a7779-marzen-reference.dts.
Based on work for the Koelsch board by Laurent Pinchart.
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Let the multiplatform Marzen support boot with the legacy DTS for
Marzen as well as the Marzen reference DTS.
Based on work for the Koelsch board by Laurent Pinchart.
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that r8a7779 has CCF support remove the legacy Marzen reference
Kconfig bits CONFIG_MACH_MARZEN_REFERENCE for the non-multiplatform
case.
Starting from this commit Marzen board support is always enabled via
CONFIG_MACH_MARZEN, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-marzen.c and board-marzen-reference.c
The file board-marzen-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.
Based on work for the Koelsch board by Laurent Pinchart.
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that the common clock framework is supported, the clock lookup
entries in clock-r8a7779.c are not registered anymore. Devices must
instead reference their clocks in the device tree. However, SCIF and CMT
devices are still instantiated through platform code, and thus need a
clock lookup entry.
Retrieve the SCIF and CMT clock entries by name and register clkdevs for
the corresponding devices. This will be removed when the SCIF and CMT
devices will be instantiated from the device tree.
Based on work for the Koelsch board by Laurent Pinchart.
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
On multiplatform kernels clocks are handled by the CCF CPG driver. It
must be explicitly initialized by a call to r8a7779_clocks_init() with
the value of the boot mode pins.
Based on similar work for the Koelsch board by Laurent Pinchart.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Marzen and r8a7779 to CONFIG_SHMOBILE_MULTI. At this
point CCF is not yet supported so you cannot run this code
yet. For CCF support to happen several different components
are needed, and this is one simple portion that moves us
forward. Other patches need to build on top of this one.
Marzen board support exists in 3 flavours:
1) SHMOBILE_MULTI, MACH_MARZEN - board-marzen-reference.c (CCF + DT)
2) SHMOBILE, MACH_MARZEN_REFERENCE - board-marzen-reference.c (DT)
3) SHMOBILE, MACH_MARZEN - board-marzen.c (legacy C code)
When CCF is done then 2) will be removed. When 1) includes same features
as 3) then 3) will be removed.
Based on work for the Koelsch and r8a7791 by Magnus Damm.
Cc: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Move the clock initialisation and OF device population from
SoC to board code. This is in keeping with the pattern used by Lager.
And the clock portion is part of decoupling clock initialisation
from SoC code in preparation for moving to the common clock framework.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
