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7146 Commits

Author SHA1 Message Date
Matt Turner
2a5d66511a MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1) 
ALIGN(x, bytes) expands to __ALIGN_MASK(x, bytes - 1), so use the one
that is most clear.

Signed-off-by: Matt Turner <mattst88@gmail.com>
To: linux-mips@linux-mips.org
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/999/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:43 +01:00
David Daney
bba9076058 MIPS: Crazy spinlock speed test. 
This is just a test program for raw_spinlocks.  The main reason I
wrote it is to validate my spinlock changes that I sent in a previous
patch.

To use it enable CONFIG_DEBUG_FS and CONFIG_SPINLOCK_TEST then at run
time do:

# mount -t debugfs none /sys/kernel/debug/
# cat /sys/kernel/debug/mips/spin_single
# cat /sys/kernel/debug/mips/spin_multi

On my 600MHz octeon cn5860 (16 CPUs) I get

		spin_single	spin_multi
base		106885		247941
spinlock_patch	75194		219465

This shows that for uncontended locks the spinlock patch gives 41%
improvement and for contended locks 12% improvement (1/time).

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/969/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:42 +01:00
David Daney
500c2e1fdb MIPS: Optimize spinlocks. 
The current locking mechanism uses a ll/sc sequence to release a
spinlock.  This is slower than a wmb() followed by a store to unlock.

The branching forward to .subsection 2 on sc failure slows down the
contended case.  So we get rid of that part too.

Since we are now working on naturally aligned u16 values, we can get
rid of a masking operation as the LHU already does the right thing.
The ANDI are reversed for better scheduling on multi-issue CPUs

On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet
forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:42 +01:00
Manuel Lauss
e275ed5ee9 MIPS: Alchemy: devboard PM needs to save CPLD registers. 
Save/restore CPLD registers when doing suspend-to-ram; this fixes issues
with harddisk and ethernet not working correctly when resuming on DB1200.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/986/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:41 +01:00
David VomLehn
81fc017954 MIPS: PowerTV: Eliminate duplicate opcode definition macros 
Change to different macros for assembler macros since the old names in
powertv_setup.c were co-opted for use in asm/asm.h. This broken the
build for the powertv platform. This patch introduces new macros based on
the new macros in asm.h to take the place of the old macro values.

Signed-off-by: David VomLehn <dvomlehn@cisco.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/985/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:41 +01:00
Ralf Baechle
3b439470e3 MIPS: Lemote 2F: Move printks out of port_access_lock. 
No point in protecting them and printks are sloow.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:41 +01:00
Ralf Baechle
7fe2d9c41d MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:41 +01:00
David Daney
541247f4d2 MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c. 
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/973/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:40 +01:00
David Daney
399614226c MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks. 
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/972/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:40 +01:00
Ralf Baechle
4837a661a5 MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:40 +01:00
Ralf Baechle
f1d39e6ed7 MIPS: Loongson: Remove pointless sample_lock from oprofile code. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:39 +01:00
Ralf Baechle
36946d7387 MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:39 +01:00
Ralf Baechle
8965087055 MIPS: i8259: Convert IRQ controller lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:38 +01:00
Ralf Baechle
598c5abad7 MIPS: IP27: Convert nmi_lock lock to arch spinlock; 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:38 +01:00
Ralf Baechle
2ba53e3712 MIPS: IP27: Remove code obfuscation by enter_panic_mode(). 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:38 +01:00
Ralf Baechle
34ee414847 MIPS: GT641xx: Convert timer lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:37 +01:00
Ralf Baechle
da4afffc1d MIPS: Alchemy: Simplify DMA channel allocation code. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Manuel Lauss <manuel.lauss@googlemail.com>
 2010-02-27 12:53:37 +01:00
Ralf Baechle
2bd0073656 MIPS: Yosemite: Convert SMP startup lock to arch spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:37 +01:00
Ralf Baechle
1a73f0478a MIPS: Alchemy: Remove time_lock. 
The sole user is au1xxx_calc_clock() which is only used in early bootup
where the is no paralellism thus no race condition to protect against.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Manuel Lauss <manuel.lauss@googlemail.com>
 2010-02-27 12:53:36 +01:00
Ralf Baechle
32baba2fb7 MIPS: DEC: Convert KN01 lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:36 +01:00
Ralf Baechle
d8d607d59e MIPS: BCM63xx: Convert timer locks to raw spinlocks. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:35 +01:00
Ralf Baechle
c45ef44f47 MIPS: PowerTV: Convert IRQ controller lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: David VomLehn <dvomlehn@cisco.com>
 2010-02-27 12:53:34 +01:00
Ralf Baechle
a963dc70a2 MIPS: Malta: Convert IRQ controller lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:32 +01:00
Ralf Baechle
ed14bbb24e MIPS: SB1480: Convert IRQ controller lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:32 +01:00
Ralf Baechle
5772f6deb6 MIPS: SB1250: Convert IRQ controller lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:32 +01:00
Ralf Baechle
f2c194a005 MIPS: GT641xx: Convert IRQ controller lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:31 +01:00
Ralf Baechle
4a41abe596 MIPS: Jazz: Convert irq controller lock to raw spinlock. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:31 +01:00
Ralf Baechle
4a8a738de6 MIPS: Make various locks static. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:30 +01:00
David Daney
86568dc41e MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts. 
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/967/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:29 +01:00
Yoichi Yuasa
d007f991a8 MIPS: Use generic ucontext.h 
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/959/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:27 +01:00
Yoichi Yuasa
7b012cee61 MIPS: Use generic serial.h 
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/960/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:27 +01:00
Yoichi Yuasa
f51e5a0772 MIPS: Use generic parport.h 
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/958/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:27 +01:00
Yoichi Yuasa
1a6e8963e0 MIPS: Use generic current.h 
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/957/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:27 +01:00
David Daney
27a5bd6457 MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs 
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/955/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:26 +01:00
David Daney
6f329468f3 MIPS: Give Octeon+ CPUs their own cputype. 
This allows us to treat them differently at runtime.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:26 +01:00
David Daney
6dd9344cfc MIPS: Implement Read Inhibit/eXecute Inhibit 
The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit
(XI) bits in the page tables work.  The upper two bits of EntryLo{0,1}
are RI and XI when the feature is enabled in the PageGrain register.
SmartMIPS only covers 32-bit systems.  Cavium Octeon+ extends this to
64-bit systems by continuing to place the RI and XI bits in the top of
EntryLo even when EntryLo is 64-bits wide.

Because we need to carry the RI and XI bits in the PTE, the layout of
the PTE is changed.  There is a two instruction overhead in the TLB
refill hot path to get the EntryLo bits into the proper position.
Also the TLB load exception has to probe the TLB to check if RI or XI
caused the exception.

Also of note is that the layout of the PTE bits is done at compile and
runtime rather than statically.  In the 32-bit case this allows for
the same number of PFN bits as before the patch as the _PAGE_HUGE is
not supported in 32-bit kernels (we have _PAGE_NO_EXEC and
_PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE).

The patch is tested on Cavium Octeon+, but should also work on 32-bit
systems with the Smart-MIPS ASE.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/952/
Patchwork: http://patchwork.linux-mips.org/patch/956/
Patchwork: http://patchwork.linux-mips.org/patch/962/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:26 +01:00
David Daney
32546f38fa MIPS: Add TLBR and ROTR to uasm. 
The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and
ROTR support in uasm.  We also add a UASM_i_ROTR macro.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/953/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:25 +01:00
David Daney
9fe2e9d6f5 MIPS: Add accessor functions and bit definitions for c0_PageGrain 
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/950/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:25 +01:00
David Daney
9b8c38917b MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels. 
64-bit CPUs have 64-bit c0_entrylo{0,1} registers.  We should use the
64-bit dmtc0 instruction to set them.  This becomes important if we
want to set the RI and XI bits present in some processors.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/954/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:25 +01:00
Frans Pop
52d7ecd033 MIPS: Remove trailing space in messages 
Signed-off-by: Frans Pop <elendil@planet.nl>
To: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/946/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:25 +01:00
Wu Zhangjin
f86a69b15f MIPS: Make the debugging of compressed kernel configurable 
This patch adds a new DEBUG_ZBOOT option to allow the users to enable it
to debug the compressed kernel support for a new board and this optoin
should be disabled to reduce the kernel image size and speed up the
kernel booting procedure when the compressed kernel support is stable.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Manuel Lauss <manuel.lauss@googlemail.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/918/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:24 +01:00
David Daney
b66bb6090d MIPS: Remove #if 0 r4k_update_mmu_cache_hwbug 
The function is #if 0ed out.  There are no other occurrences of its
name in the tree.  It is safe to remove.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/936/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:23 +01:00
Yoichi Yuasa
ab4ba29168 MIPS: TXx9: Remove forced serial console setting 
It is not always used, even if it is available.

Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/933/
Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:22 +01:00
Alexander Clouter
7084338eb8 MIPS: AR7: Make ar7_register_devices much more durable 
[Ralf: Fixed up the rejects and changed all the new printk(KERN_...); to
pr_xxx() as suggested by Wu.]

Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/920/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:22 +01:00
Alexander Clouter
632b629c0c MIPS: AR7: Fix USB slave mem range typo 
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/919/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:22 +01:00
Alexander Clouter
4d1da8c296 MIPS: AR7: Whitespace hacking 
[Ralf: Fixed up reject and Wu's complaints about comment style.]

Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/921/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:21 +01:00
Yoichi Yuasa
10229f3761 MIPS: Alchemy: Use strlcat() for the command line arguments 
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/928/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:21 +01:00
Yoichi Yuasa
ae7cbef5e5 MIPS: Alchemy: Remove prom_getcmdline() 
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/927/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:21 +01:00
Yoichi Yuasa
c63d0cb5fe MIPS: Alchemy: Remove forced command line setting 
It is not always used, even if it is available.

Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/893/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:20 +01:00
David Daney
368bf8ef30 MIPS: Set __elf_platform for Octeon. 
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/892/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:20 +01:00