Merge "mvebu SoC changes for v3.17" from Jason Cooper:
- kirkwood
* add setup file for netxbig LEDs (non-trivial DT binding doesn't exist yet)
- mvebu
* staticize where needed
* add CPU hotplug for Armada XP
* add public datasheet for Armada 370
* don't apply thermal quirk by default
* get SoC ID from the system controller when possible
* tag 'mvebu-soc-3.17' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Staticize mvebu_cpu_reset_init
ARM: mvebu: Staticize armada_370_xp_cpu_pm_init
ARM: mvebu: Staticize armada_375_smp_cpu1_enable_wa
ARM: mvebu: Use system controller to get the soc id when possible
ARM: mvebu: Use the a standard errno in mvebu_get_soc_id
ARM: mvebu: Don't apply the thermal quirk if the SoC revision is unknown
Documentation: arm: add URLs to public datasheets for the Marvell Armada 370 SoC
ARM: mvebu: implement CPU hotplug support for Armada XP
ARM: mvebu: export PMSU idle enter/exit functions
ARM: mvebu: slightly refactor/rename PMSU idle related functions
ARM: mvebu: remove stub implementation of CPU hotplug on Armada 375/38x
ARM: Kirkwood: Add setup file for netxbig LEDs
ARM: mvebu: mark armada_370_xp_pmsu_idle_prepare() as static
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "First pull request of Versatile family clean-ups for v3.17" from Linus
Walleij:
- Remove <mach/memory.h> from the Integrator, paving the
road for multiplatform.
- Push the CLCD helper code down into the framebuffer subsystem,
removing the last hook in plat-versatile for the Integrator,
also paving the road for multiplatform.
Patches tested on Integrator/AP, Integrator/CP and Versatile AB
(all real hardware).
* tag 'versatile-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
video: move Versatile CLCD helpers
ARM: integrator: get rid of <mach/memory.h>
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Renesas ARM Based SoC Boards Updates for v3.17" from Simon Horman:
- armadillo800eva LED support
- Remove now unnecessary work arounds for c\lock issues
- Enable R-Car Gen2 CMA code
* tag 'renesas-boards-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable R-Car Gen2 CMA code in board files
ARM: shmobile: armadillo800eva reference: Spelling s/ED/LED/
ARM: shmobile: armadillo800eva legacy: Add LED support
ARM: shmobile: lager-reference: Remove workarounds for core clock issues
ARM: shmobile: koelsch-reference: Remove workarounds for core clock issues
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Renesas ARM Based SoC Updates for v3.17" from Simon Horman:
- Use shmobile_init_late on r8a7791 and r8a7790 whien booting using DT-only
- Support Core-Standby for Suspend to RAM on r8a7791 and r8a7790 SoCs
- Shared CMA reservation for R-Car Gen2 SoCs
- Add r8a7791 SYSC power management support
* tag 'renesas-soc-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Remove ARCH_HAS_CPUFREQ config for shmobile
ARM: shmobile: rcar-gen2: update call to dma_contiguous_reserve_area
ARM: shmobile: rcar-gen2: correct return value of shmobile_smp_apmu_suspend_init
ARM: shmobile: rcar-gen2: Remove useless copied section for LongTrail
ARM: shmobile: rcar-gen2: Use "1ULL" instead of "(u64)1"
ARM: shmobile: rcar-gen2: Update for of_get_flat_dt_prop() update
ARM: shmobile: Add shared R-Car Gen2 CMA reservation code
ARM: shmobile: Use shmobile_init_late() on r8a7791 DT-only
ARM: shmobile: Use shmobile_init_late() on r8a7790 DT-only
ARM: shmobile: Mark all SoCs in shmobile as CPUFreq, capable
ARM: shmobile: r8a7791: Support Core-Standby for Suspend to RAM
ARM: shmobile: r8a7790: Support Core-Standby for Suspend to RAM
ARM: shmobile: APMU: Add Core-Standby-state for Suspend to RAM
ARM: shmobile: r8a7791 SYSC setup code
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "DT IRQ and clock support for Versatile platforms" from Rob Herring.
This branch moves IRQ and clock support over to DT for the versatile
platforms.
* tag 'versatile-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
clk: versatile: add versatile OSC support
dts: versatile: add clock tree
ARM: timer-sp: allow getting timer1 clock from DT to fallback to legacy clock
dt/bindings: add compatible string for versatile osc clock
dt/bindings: arm-boards: add binding for Versatile core module
dts: versatile: add pl180 compatible strings
ARM: versatile: remove init_irq hook for DT boot
ARM: integrator: convert to use irqchip_init
irqchip: versatile-fpga: add support for arm,versatile-sic
irqchip: versatile-fpga: Add IRQCHIP_DECLARE support
dts: versatile: add missing irq controller properties
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
Let's say clock A and B are two gate clocks that share the same register
bit in hardware. Therefore they are registered as shared gate clocks
with imx_clk_gate2_shared().
In a scenario that only clock A is enabled by clk_enable(A) while B is
not used, the shared gate will be unexpectedly disabled in hardware.
It happens because clk_enable(A) increments the share_count from 0 to 1,
while clock B is unused to clock core, and therefore the core function
will just disable B by calling clk->ops->disable() directly. The
consequence of that call is share_count is decremented to 0 and the gate
is disabled in hardware, even though clock A is still in use.
The patch fixes the issue by initializing the share_count per hardware
state and returns enable state per share_count from .is_enabled() hook,
in case it's a shared gate.
While at it, add a check in clk_gate2_disable() to ensure it's never
called with a zero share_count.
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Fixes: f9f28cdf21 ("ARM: imx: add shared gate clock support")
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Samsung fixes-2 for v3.16" from Kukjin Kim:
- fix the check for SMP configuration with using CONFIG_SMP
not just SMP
- fix the number of pwm-cells for exynos4 pwm
- fix ftrace for exynos_mct
- register exynos_mct for stable udely
- fix secondary boot addr for secure mode for exynos SoCs
* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Update secondary boot addr for secure mode
clocksource: exynos_mct: Register the timer for stable udelay
clocksource: exynos_mct: Fix ftrace
ARM: dts: fix pwm-cells in pwm node for exynos4
ARM: EXYNOS: Fix the check for non-smp configuration
Signed-off-by: Olof Johansson <olof@lixom.net>
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.
The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.
Signed-off-by: Tushar Behera <tushar.b@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reported-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
It's 1.6 GHz for the Cortex-A15.
Avoids warnings like "/cpus/cpu@0 missing clock-frequency property".
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Almost all Exynos-series of SoCs that run in secure mode don't need
additional offset for every CPU, with Exynos4412 being the only
exception.
Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420).
While at it, fix the coding style (space around *).
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Tested-by: Andreas Faerber <afaerber@suse.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch removes supporting codes for s5p6440 and s5p6450 because
seems no more used now. And if its supporting is required, DT based
codes should be supprted next time.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The revision checking in l2c310_enable() was not correct; we were
masking the part number rather than the revision number. Fix this
to use the correct macro.
Fixes: 4374d64933 ("ARM: l2c: add automatic enable of early BRESP")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
As this board use external clock for RMII interface we should specify 'rmii'
phy mode and 'rmii-clock-ext' to make ethernet working.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently, child nodes of the gpmc node are iterated and probed
regardless of their 'status' property. This means adding 'status =
"disabled";' has no effect.
This patch changes the iteration to only probe nodes marked as
available.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The DSP platform device for TI DSP/Bridge is currently
created unconditionally whenever CONFIG_TIDSPBRIDGE is
enabled. This device should only be created on OMAP34xx/
OMAP36xx SoCs, and not for other OMAP3 derived SoCs or when
booting multi-arch images on other SoCs. So, add a check for
the SoC family both before creating the device and allocating
the carveout memory for the device.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
After clarification from the hardware team it was found that
this 1.8V PHY supply can't be switched OFF when SoC is Active.
Since the PHY IPs don't contain isolation logic built in the design to
allow the power rail to be switched off, there is a very high risk
of IP reliability and additional leakage paths which can result in
additional power consumption.
The only scenario where this rail can be switched off is part of Power on
reset sequencing, but it needs to be kept always-on during operation.
This patch is required for proper functionality of USB, SATA
and PCIe on DRA7-evm.
CC: Rajendra Nayak <rnayak@ti.com>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
omap44xx_restart is defined as a static void inline when DRA7/AM437X is
defined alone, which implies that the restart function is no longer
functional even though it is built in. So, fix the definition of the
same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
A struct member variable is set to the same value more than once
This was found using a static code analysis program called cppcheck.
Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds the STMicroelectonics MEMS sensor devices to the Ux500
family device trees:
- Accelerometer
- Magnetometer
- Gyroscope
- Pressure (barometer)
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Denis CIOCCA <denis.ciocca@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds some missing DMA channel information to the disabled
MMC/SD/SDIO blocks number 3 and 5, and notes that the assignment
of MSP channels vary with ASIC variant.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a VCC and VIO regulator supplies to the the STMPE expander
found on the STUIB UIB variants.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A23 has the same MMIO reset controllers matching the clocks gates,
just like in the A31. This patch adds the reset controller nodes and
the reset control phandles for the peripherals needing them to the
DTSI.
Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for
ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some
additions to the machine code. It is used to support the hstimer.
However the hstimer on sun8i only has 1 timer, which is somewhat
useless. Support for it will probably not be added. Hence the
decision to use sun6i-a31-clock-reset here to avoid the changes to
sun8i machine code.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Select the MFD_SUN6I_PRCM option when sun8i arch is enabled in order to
get the PRCM (Power/Reset/Clock Management) related drivers compiled.
Also select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER to make sure
the reset controller drivers are compiled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Merge "ARM: tegra: use us counter as delay timer" from Stephen Warren:
Tegra has a micro-second counter whose rate doesn't vary with cpufreq
changes. Register it so it can be used as the delay timer, so delays
aren't influenced by cpufreq.
* tag 'tegra-for-3.17-delay-timer' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clocksource: tegra: Use us counter as delay timer
ARM: choose highest resolution delay timer
kernel: add calibration_delay_done()
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Renesas ARM Based SoC Cleanup for v3.17" from Simon Horman:
- Use shmobile_init_delay on r8a7790, r7s72100 and EMEV2 SoCs
- Remove unused redundant callbacks on EMEV2 SoC
* tag 'renesas-soc-cleanup-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Remove unused r8a7790_init_early()
ARM: shmobile: Use r8a7790 DT CPU Frequency for Lager
ARM: shmobile: Use r8a7790 DT CPU Frequency in common case
ARM: shmobile: Use shmobile_init_delay() on r7s72100
ARM: shmobile: Use shmobile_init_delay() on Genmai boards
ARM: shmobile: Update r7s72100 DTS to include CPU frequency
ARM: shmobile: Get rid of redundant EMEV2 mach callbacks
ARM: shmobile: Use shmobile_init_delay() on EMEV2
ARM: shmobile: Update EMEV2 DTS to include CPU frequency
Signed-off-by: Olof Johansson <olof@lixom.net>
Pull "Renesas ARM Based SoC r8a7779-multiplatform Updates for v3.17" from
Simon Horman:
Move r8a7779 SoC and its Marzen board to use common clocks,
multiplatform and initialise SCIF (serial) devices using DT.
* tag 'renesas-r8a7779-multiplatform-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits)
ARM: shmobile: marzen: Do not use workaround for scif devices
ARM: shmobile: marzen: Initialise SCIF devices using DT
ARM: shmobile: marzen: Remove early_printk from command line
ARM: shmobile: r8a7779: Add scif nodes to dtsi
ARM: shmobile: r8a7779 dtsi: Correct #address-cells/#size-cells for clocks
ARM: shmobile: r8a7779 dtsi: Update unit-addresses for clocks
ARM: shmobile: r8a7779: Remove unused r8a7779_init_delay()
ARM: shmobile: marzen-reference: Use DT CPU Frequency
ARM: shmobile: r8a7779: Use DT CPU Frequency in common case
ARM: shmobile: r8a7779: Add Maximum CPU Frequency to DTS
ARM: shmobile: marzen-reference: Remove legacy clock support
ARM: shmobile: Remove Marzen reference DTS
ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB
ARM: shmobile: Remove non-multiplatform Marzen reference support
ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU
ARM: shmobile: marzen-reference: Initialize CPG device
ARM: shmobile: r8a7779: Initial multiplatform support
ARM: shmobile: marzen-reference: Move clock and OF device initialisation into board code
ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to clock-r8a7779.c
ARM: shmobile: r8a7779: Add helper to read mode pins
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Renesas ARM Based SoC Defconfig Updates for v3.17" from Simon Horman:
* Enable Marzen board and r8a7779 SoC, CPUFREQ and PM_RUNTIME in
shmobile (multiplatform) defconfig
* Enable LED support in armadillo800eva defconfig
* tag 'renesas-defconfig-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable CPUFREQ configuration
ARM: shmobile: Enable PM_RUNTIME in defconfig
ARM: shmobile: marzen: Add to shmobile defconfig
ARM: shmobile: armadillo800eva defconfig: Enable REGULATOR_GPIO and LEDS_GPIO
Merge "Renesas ARM Based SoC Cpufreq Updates for v3.17" from Simon Horman
* Add cpufreq-cpu0 device registration
* tag 'renesas-cpufreq-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: add cpufreq-cpu0 driver for common SH-Mobile
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Renesas ARM Based SoC Header Cleanup for v3.17" from Simon Horman:
Move the most common shared header files for mach-shmobile
from <mach/foobar.h> to "foobar.h"
* tag 'renesas-header-cleanup-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Move rcar-gen2.h, cleanup r8a7790 case
ARM: shmobile: Move pm-rcar.h, cleanup r8a7779 case
ARM: shmobile: Move pm-rmobile.h, cleanup sh73xx.h
ARM: shmobile: Move common.h
ARM: shmobile: Move most of irqs.h, keep some for pinctl
ARM: shmobile: Move clock.h
ARM: shmobile: Move dma-register.h
ARM: shmobile: Move intc.h, cleanup sh_intc.h usage
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Renesas ARM Based SoC Clock Updates for v3.17" from Simon Horman:
- Fix device node reference leakage in shmobile_init_delay
* tag 'renesas-clock-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Fix device node reference leakage in shmobile_init_delay
Signed-off-by: Olof Johansson <olof@lixom.net>
clps711x_devices_init() can be used directly in ".machine_init"
without any intermediate function.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add initialization of commonly used devices to the CLEP7312 generic
board.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch removes old support for cpuidle and switches all current
users to use new cpuidle driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
One more step to allowing CLPS711X to participate in the
multi-platform defconfig.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
All uses of the IO_ADDRESS() macro has been removed.
This patch removes the definition of this macro.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
The NVIDIA Tegra 3 based Apalis T30 module contains an Intel i210 resp.
i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller, PWM
LEDs generically accessible from user space and an LM95245 temperature
sensor chip. The later three can also be found on the Colibri T30
module.
While at it move the NEON entry down to its proper place to have it all
nicely ordered again.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The divider value provided to the _dpll_test_fint can reach value of
256 with J type DPLLs (USB etc.), which causes an overflow with the u8
datatype. Fix this by changing the parameter to be an int instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: changed type of 'n' to unsigned int]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the sysconfig class bits for the Super Speed USB
controllers
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Get rid of optional clock as that is now managed by the
AHCI platform driver.
Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
