support pfuze200 chip which remove SW1C and SW4 based on pfuze100.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Reserved memory nodes allow for the reservation of static (fixed
address) regions, or dynamically allocated regions for a specific
purpose.
[joshc: Based on binding document proposed (in non-patch form) here:
http://lkml.kernel.org/g/20131030134702.19B57C402A0@trevor.secretlab.ca
adapted to support #memory-region-cells]
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
[mszyprow: removed #memory-region-cells property]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[grant.likely: removed residual #memory-region-cells example]
Signed-off-by: Grant Likely <grant.likely@linaro.org>
The Synology NAS devices use a very similar mechanism to QNAP NAS
devices to power off. Both send a single charactor command to a PIC,
over the second serial port. However the baud rate and the command
differ. Generalize the driver to support this.
Signed-off-by: Ben Peddell <klightspeed@killerwolves.net>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Cc: Anton Vorontsov <anton@enomsg.org>
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Pull clk framework fixes from Mike Turquette:
"Clock framework and driver fixes, all of which fix user-visible
regressions.
There is a single framework fix that prevents dereferencing a NULL
pointer when calling clk_get. The range of fixes for clock driver
regressions spans memory leak fixes, touching the wrong registers that
cause things to explode, misconfigured clock rates that result in
non-responsive devices and even some boot failures. The most benign
fix is DT binding doc typo. It is a stable ABI exposed from the
kernel that was introduced in -rc1, so best to fix it now"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: (25 commits)
clk:at91: Fix memory leak in of_at91_clk_master_setup()
clk: nomadik: fix multiplatform problem
clk: Correct handling of NULL clk in __clk_{get, put}
clk: shmobile: Fix typo in MSTP clock DT bindings
clk: shmobile: rcar-gen2: Fix qspi divisor
clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocks
clk: tegra124: remove gr2d and gr3d clocks
clk: tegra: Fix vic03 mux index
clk: shmobile: rcar-gen2: Fix qspi divisor
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: tegra: use max divider if divider overflows
clk: tegra: cclk_lp has a pllx/2 divider
clk: tegra: fix sdmmc clks on Tegra1x4
clk: tegra: fix host1x clock on Tegra124
clk: tegra: PLLD2 fixes for hdmi
clk: tegra: Fix PLLD mnp table
clk: tegra: Fix PLLP rate table
clk: tegra: Correct clock number for UARTE
clk: tegra: Add missing Tegra20 fuse clks
ARM: keystone: dts: fix clkvcp3 control register address
...
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need poking, which are per phy, but shared between the
ohci and ehci controllers, so these are also controlled from this new phy
driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: David S. Miller <davem@davemloft.net>
---
v3: Remove stray empty line at end of socfpga_cyclone5_socdk.dts
v2: Use the dwmac-sti as an example for a glue layer and split patch up
to have dts as a separate patch. Also cc dts maintainers since there is
a new binding.
Add Dynamic Memory Manager (DMM) bindings for OMAP4 and OMAP5 and DRA7x devices.
DMM only requires address and irq information.
Add documentation for the DMM bindings.
Originally worked on by Andy Gross <andygro@gmail.com>
Cc: Andy Gross <andygro@gmail.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Pull slave-dma fixes from Vinod Koul:
"This request brings you two small fixes. First one for fixing
dereference of freed descriptor and second for fixing sdma bindings
for it to work for imx25.
I was planning to send this about 10days ago but then I had to proceed
on my paternity leave and didnt get chance to send this. Now got a
bit of time from dady duties :)"
* 'fixes' of git://git.infradead.org/users/vkoul/slave-dma:
dma: sdma: Add imx25 compatible
dma: ste_dma40: don't dereference free:d descriptor
The pmu is needed to bring up the cores during smp operations and later
also other system parts. Therefore add a node and documentation for it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Add dt-nodes for the sram on rk3066 and rk3188 including the reserved section
needed for smp bringup.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This binding
document describes the bindings for both of them since the bindings are very
similar.
Each of them needs:
* A address range where the registers are mapped
* An interrupt number for the device interrupt
* A clock. For the the ZYNQ hardmacro interface this is the modules PCAP
clock, for the AXI softmacro it is the AXI bus interface clock.
Additionally the bindings specify whether an external multiplexer is used and in
which mode it is used. The devicetree bindings also describe which external
channels are connected and in which configuration.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Add bindings for TI Async External Memory Interface (AEMIF) controller.
The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
provide a glue-less interface to a variety of asynchronous memory devices like
ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
can be accessed via 4 chip selects with 64M byte access per chip select.
We are not encoding CS number in reg property, it's memory partition number.
The CS number is encoded for Davinci NAND node using standalone property
"ti,davinci-chipselect" and we need to provide two memory ranges to it,
as result we can't encode CS number in "reg" for AEMIF child devices
(NAND/NOR/etc), as it will break bindings compatibility.
In this patch, NAND node is used just as an example of child node.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Some SoCs need parts of their sram for special purposes. So while being part
of the peripheral, it should not be part of the genpool controlling the sram.
Therefore add the option to define reserved regions as subnodes of the
sram-node similar to defining reserved global memory regions.
Originally
Suggested-by: Rob Herring <robherring2@gmail.com>
Using subnodes for reserved regions
Suggested-by: Grant Likely <grant.likely@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add device tree binding documentation for Texas Instrument's wl1251
wireless lan chip. For now only the SPI binding is documented.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Some gpio-leds need retain the state even in suspend, such as charger led.
But this property missed in devicetree, add it.
(cooloney@gmail.com: fold DT binding updates into this patch)
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Bryan Wu <cooloney@gmail.com>
This patch adds devicetree support for the MC13XXX LED driver.
(cooloney@gmail.com: remove unneeded semicolon)
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Bryan Wu <cooloney@gmail.com>
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
Documentation:
- Add missing "interrupt-parent", "#address-cells", "#size-cells", and
"clocks" properties,
- Add missing default values for "num-cs", "renesas,tx-fifo-size" and
"renesas,rx-fifo-size",
- Add a reference to the pinctrl documentation.
Implementation:
- As "num-cs" is marked optional, provide a sensible default.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
This driver supports the GPIO controller found in LSI ZEVIO SoCs.
It has been successfully tested on a TI nspire CX calculator.
Signed-off-by: Fabian Vogt <fabian@ritter-vogt.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document what we (Laurent and I, following a mailing list dicussion)
believe are best practices for the polarity flag in a GPIO specifier.
While touching the doc, I made a few minor editing changes to other
areas.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Updates from Jean-Fracois for the TDA998x driver, which are on top of
the fixes you have previously pulled, except these changes aren't
intended for -rc, but the next merge window.
Several of these are issues of correctness - passing more correct HDMI
info packets, not reading registers in older chips documented as write
only (despite appearing to be read/write in later chips). Others are
code cleanups (using definitions rather than constants where we have
them already in the kernel).
Additional functionality is also added by way of optional support for
the IRQ from the TDA998x, which allows us to avoid busy-waiting for
the EDID reads.
* 'tda998x-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-cubox:
drm/i2c: tda998x: always use the same device for all kernel messages
drm/i2c: tda998x: adjust the audio clock divider for S/PDIF
drm/i2c: tda998x: code optimization
drm/i2c: tda998x: remove the unused variable ca_i2s
drm/i2c: tda998x: make the audio code more readable
drm/i2c: tda998x: use irq for connection status and EDID read
drm/i2c: tda998x: always enable EDID read IRQ
drm/i2c: tda998x: add DT documentation
drm/i2c: tda998x: add DT support
drm/i2c: tda998x: don't read write-only registers
drm/i2c: tda998x: don't freeze the system at audio startup time
drm/i2c: tda998x: change probe message origin
drm/i2c: tda998x: code cleanup
drm/i2c: tda998x: clean up error chip version checking
drm/i2c: tda998x: check more I/O errors
drm/i2c: tda998x: simplify the i2c read/write functions
drm/i2c: tda998x: use ALSA IEC958 definitions and update audio frequency
drm/i2c: tda998x: add the active aspect in HDMI AVI frame
drm/i2c: tda998x: use HDMI constants
This reverts tlv320aic32x4 as compatible for tlv320aic3x as it has its
own bindings now.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.
Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.
Finally, fix an indentation error for the sysmgr node.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>
This patch adds support for the new v2 version of the axi-clkgen core.
Unfortunately the method of accessing the registers is quite different on v2,
while the content still stays largely the same. So the patch adds a small
abstraction layer which implements the specific read and write functions for v1
and v2 in callback functions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
While we are here, also brush up the devicetree binding documentation.
The example was an inappropriate copy from the sh_mobile driver.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Add support for the led-mode property for the following PHYs
which have a single LED mode configuration value.
KSZ8001 and KSZ8041 which both use register 0x1e bits 15,14 and
KSZ8021, KSZ8031 and KSZ8051 which use register 0x1f bits 5,4
to control the LED configuration.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Dove pinctrl binding now requires three different reg properties. This
updates corresponding binding and example accordingly. While at it, also
document reg property as required for the other MVEBU SoC pinctrl nodes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Marvell Dove SoC binding was not documented, yet. Add the documentation
and also describe Global Configuration register node in it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Merge "mvebu new SoCs for v3.15" from Jason Cooper:
- mvebu
- initial support for Armada 375, 380, and 385
Depends:
- tags/mvebu-soc-3.15 (resolves delete/rename hidden conflict)
* tag 'mvebu-soc-3xx-3.15' of git://git.infradead.org/linux-mvebu:
Documentation: arm: update Marvell documentation about Armada 375/38x
ARM: mvebu: add initial support for the Armada 380/385 SOCs
ARM: mvebu: add workaround for data abort issue on Armada 375
ARM: mvebu: add initial support for the Armada 375 SOCs
ARM: mvebu: add Armada 375 support to the system-controller driver
ARM: mvebu: make CPU_PJ4B selection a per-SoC choice
ARM: mvebu: rename DT machine structure for Armada 370/XP
ARM: mvebu: rename armada-370-xp.c to board-v7.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mvebu watchdog driver changes for v3.15
- orion watchdog
- cleanup and extend driver to support Armada 370 and Armada XP
Depends:
- tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx)
- both are based on v3.14-rc1
* tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu:
watchdog: orion: Enable the build on ARCH_MVEBU
watchdog: orion: Add support for Armada 370 and Armada XP SoC
watchdog: orion: Add per-compatible watchdog start implementation
watchdog: orion: Add per-compatible clock initialization
watchdog: orion: Introduce per-compatible of_device_id data
watchdog: orion: Introduce an orion_watchdog device structure
watchdog: orion: Remove unneeded BRIDGE_CAUSE clear
watchdog: orion: Make RSTOUT register a separate resource
watchdog: orion: Handle the interrupt so it's properly acked
watchdog: orion: Make sure the watchdog is initially stopped
watchdog: orion: Remove unused macros
watchdog: orion: Use atomic access for shared registers
watchdog: orion: Add clock error handling
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
