Add qeth device private ioctl to query the OSA address table.
This helps debugging hw related problems.
Signed-off-by: Frank Blaschka <frank.blaschka@de.ibm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
SAL specification mandates that ia64_mca_log_sal_error_record() gets
called with interrupts enabled, and that's why ia64_mca_cmc_int_handler()
is enabling them. It however forgets to re-disable them when exiting,
which triggers WARN_ON() in generic IRQ handler.
Disable the interrupts again before exiting. This is analogous to
a396768574 ("[IA64] disable interrupts at end of ia64_mca_cpe_int_handler()").
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Add a remoteproc driver for OMAP4, so we can boot the dual-M3 and
and DSP subsystems.
Use the omap_device_* API to control the hardware state, and utilize
the OMAP mailbox to interrupt the remote processor when a new message
is pending (the mailbox payload is used to tell it which virtqueue was
the message placed in).
Conversely, when an inbound mailbox message arrives, tell the remoteproc
core which virtqueue is triggered.
Later we will also use the mailbox payload to signal omap-specific
events like remote crashes (which will be used to trigger remoteproc
recovery) and power management transitions. At that point we will also
extend the remoteproc core to support this.
Based on (but now quite far from) work done by Fernando Guzman Lugo
<fernando.lugo@ti.com> and Hari Kanigeri <h-kanigeri2@ti.com>.
Designed with Brian Swetland <swetland@google.com>.
Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Brian Swetland <swetland@google.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Greg KH <greg@kroah.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
WARNING: arch/arm/mach-omap2/built-in.o(.text+0xeae8):
Section mismatch in reference from the function cm_t35_init_usbh()
to the (unknown reference) .init.data:(unknown)
The function cm_t35_init_usbh() references
the (unknown reference) __initdata (unknown).
This is often because cm_t35_init_usbh lacks a __initdata
annotation or the annotation of (unknown) is wrong.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the latest Sourcery G++ Lite 2011.03-41 and latest linaro
tool-chains OMAP2 only build breaks with below error.
arch/arm/mach-omap2/omap-smc.S: Assembler messages:
arch/arm/mach-omap2/omap-smc.S:30: Error: selected processor does not support ARM mode `smc #0'
arch/arm/mach-omap2/omap-smc.S:53: Error: selected processor does not support ARM mode `smc #0'
arch/arm/mach-omap2/omap-smc.S:61: Error: selected processor does not support ARM mode `smc #0'
arch/arm/mach-omap2/omap-smc.S:69: Error: selected processor does not support ARM mode `smc #0'
arch/arm/mach-omap2/omap-smc.S:77: Error: selected processor does not support ARM mode `smc #0'
make[1]: *** [arch/arm/mach-omap2/omap-smc.o] Error 1
OMAP2 devices doesn't have the security support but the security support
was getting built because of OMAP2PLUS. Don't build security code for
OMAP2 devices.
While at it, fix the secure-common line in the Makefile to use tabs
instead of spaces.
Reported-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The new PMC driver now configures the PMU interrupt inversion, so board
files don't need to poke the PMC registers directly to achieve this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
fbdev fixes for 3.3
It includes:
- compile fix for fsl-diu-fb
- fix for a suspend/resume issue in atmel_lcdfb
- fix for a suspend/resume issue in OMAP
- workaround for a hardware bug to avoid physical damage in OMAP
- really trivial dead code removal in intelfb
* tag 'fbdev-fixes-for-3.3-1' of git://github.com/schandinat/linux-2.6:
atmel_lcdfb: fix usage of CONTRAST_CTR in suspend/resume
intelfb: remove some dead code
drivers/video: compile fixes for fsl-diu-fb.c
OMAPDSS: HDMI: PHY burnout fix
OMAP: 4430SDP/Panda: add HDMI HPD gpio
OMAP: 4430SDP/Panda: setup HDMI GPIO muxes
OMAPDSS: remove wrong HDMI HPD muxing
OMAP: 4430SDP/Panda: rename HPD GPIO to CT_CP_HPD
OMAP: 4430SDP/Panda: use gpio_free_array to free HDMI gpios
OMAPDSS: use sync versions of pm_runtime_put
* 'mxs/clk' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: Use a proper timeout mechanism
ARM: mx28: check for gated clocks when setting saif divider
arm/mxs: Add support for SSP/MMC ports 2 & 3
* 'ux500-timers' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: plat-nomadik: modernize MTU timer
ARM: plat-nomadik: handle clocking properly
ARM: plat-nomadik: get rid of global mtu base pointer
There were conflicts between fixes going in after 3.3-rc1 and
Russell's stable arm-soc base branch. Resolving it in the dependency
branch so that each topic branch shares the same resolution.
Conflicts:
arch/arm/mach-at91/at91cap9.c
arch/arm/mach-at91/at91sam9g45.c
arch: fix ioport mapping on mips,sh
Kevin Cernekee reported that recent cleanup that replaced pci_iomap with
a generic function failed to take into account the differences in io
port handling on mips and sh architectures.
Rather than revert the changes reintroducing the code duplication, this
patchset fixes this by adding ability for architectures to override
ioport mapping for pci devices.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost:
sh: use the the PCI channels's io_map_base
mips: use the the PCI controller's io_map_base
lib: add NO_GENERIC_PCI_IOPORT_MAP
The following patch fixes a bug introduced by the following
commit:
e050e3f0a7 ("perf: Fix broken interrupt rate throttling")
The patch caused the following warning to pop up depending on
the sampling frequency adjustments:
------------[ cut here ]------------
WARNING: at arch/x86/kernel/cpu/perf_event.c:995 x86_pmu_start+0x79/0xd4()
It was caused by the following call sequence:
perf_adjust_freq_unthr_context.part() {
stop()
if (delta > 0) {
perf_adjust_period() {
if (period > 8*...) {
stop()
...
start()
}
}
}
start()
}
Which caused a double start and a double stop, thus triggering
the assert in x86_pmu_start().
The patch fixes the problem by avoiding the double calls. We
pass a new argument to perf_adjust_period() to indicate whether
or not the event is already stopped. We can't just remove the
start/stop from that function because it's called from
__perf_event_overflow where the event needs to be reloaded via a
stop/start back-toback call.
The patch reintroduces the assertion in x86_pmu_start() which
was removed by commit:
84f2b9b ("perf: Remove deprecated WARN_ON_ONCE()")
In this second version, we've added calls to disable/enable PMU
during unthrottling or frequency adjustment based on bug report
of spurious NMI interrupts from Eric Dumazet.
Reported-and-tested-by: Eric Dumazet <eric.dumazet@gmail.com>
Signed-off-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: markus@trippelsdorf.de
Cc: paulus@samba.org
Link: http://lkml.kernel.org/r/20120207133956.GA4932@quad
[ Minor edits to the changelog and to the code ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Stephane Eranian reported that doing a scheduler latency
measurements with perf on AMD doesn't work out as expected due
to the fact that the sched_clock() granularity is too coarse,
i.e. done in jiffies due to the sched_clock_stable not set,
which, if set, would mean that we get to use the TSC as sample
source which would give us much higher precision.
However, there's no reason not to set sched_clock_stable on AMD
because all families from F10h and upwards do have an invariant
TSC and have the CPUID flag to prove (CPUID_8000_0007_EDX[8]).
Make it so, #1.
Signed-off-by: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bp@amd64.org>
Cc: Venki Pallipadi <venki@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
Link: http://lkml.kernel.org/r/20120206132546.GA30854@quad
[ Should any non-standard system break the TSC, we should
mark them so explicitly, in their platform init handler, or
in a DMI quirk. ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit simply cleans up the style used in this file to fall
in line with what's specified in CodingStyle. Mostly comment
changes, with a single removal of unneeded braces.
Note that the comments for all the DMI quirks in
reboot_dmi_table now all line up consistently using tabs instead
of spaces.
Signed-off-by: Michael D Labriola <michael.d.labriola@gmail.com>
Link: http://lkml.kernel.org/n/tip-lde9yy7qsomh0sdqevn7xp56@git.kernel.org
[ Fixed a few small details. ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit reduces the X86_32 reboot_dmi_table and the X86_64
pci_reboot_dmi_table into a single table with a single set of
functions (e.g., only 1 call to core_initcall).
The table entries that use set_bios_reboot are grouped together
inside a #define CONFIG_X86_32 block.
Note that there's a single entry that uses set_kbd_reboot, which
used to be available only on X86_32. This commit moves that
entry outside the X86_32 block because it seems it never should
have been in there. There's multiple places in reboot.c that
assume KBD is valid regardless of X86_32/X86_64.
Signed-off-by: Michael D Labriola <michael.d.labriola@gmail.com>
Cc: Matthew Garrett <mjg@redhat.com>
Link: http://lkml.kernel.org/n/tip-lv3aliubas2l3aenq8v3uklk@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
The definition of it being questionable already (unnecessarily
including a cast), and it being used in a single place that can
be written shorter without it, remove this #define.
Along the same lines, simplify __ticket_spin_is_locked()'s main
expression, which was the more convoluted way because of needs
that went away with the recent type changes by Jeremy.
This is pure cleanup, no functional change intended.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/4F2C06020200007800071066@nat28.tlf.novell.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This adds the wifi led bound to the rfkill0 event to the device
tree of paz00.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds the wakeup gpio which is connected to the embedded
controller to the device tree of paz00.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the ADT7461 temperature monitoring IC which is connected via
the DVC controller.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The power gpio for the external memory card was specified wrongly.
Replace it with the correct value (tested with warmboot with fastboot).
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This PMC driver is enough to parse the nvidia,invert-interrupt property
from device tree, and configure the PMC's to honor that.
In the future, this file could expand to centralize all other PMC accesses
within the mach-tegra code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit d91eeb0 "ARM: tegra: emc: device tree support" modified the EMC
driver to create an EMC table from existing register settings when none
was provided through platform data or device tree. This code wrote the
wrong clock rate into the table; the actual rate in Hz, rather than the
expected half-rate in KHz. This caused the BUG_ON in
tegra2_emc_clk_round_rate() to fire, since that enormous rate could not
be generated.
Fixes:
[ 2.425921] kernel BUG at arch/arm/mach-tegra/tegra2_clocks.c:1158!
...
[ 2.618766] [<c001c0e8>] (tegra2_emc_clk_round_rate+0x58/0x70) from [<c00198b4>] (clk_round_rate+0x48/0x68)
[ 2.628494] [<c00198b4>] (clk_round_rate+0x48/0x68) from [<c0019cc0>] (clk_set_rate_locked+0x40/0x68)
[ 2.637707] [<c0019cc0>] (clk_set_rate_locked+0x40/0x68) from [<c0019d10>] (clk_set_rate+0x28/0x40)
[ 2.646754] [<c0019d10>] (clk_set_rate+0x28/0x40) from [<c001ffc8>] (tegra_update_cpu_speed+0x54/0x144)
[ 2.656144] [<c001ffc8>] (tegra_update_cpu_speed+0x54/0x144) from [<c002016c>] (tegra_target+0xb4/0xe0)
[ 2.665538] [<c002016c>] (tegra_target+0xb4/0xe0) from [<c01a96c0>] (__cpufreq_driver_target+0x88/0xa4)
[ 2.674931] [<c01a96c0>] (__cpufreq_driver_target+0x88/0xa4) from [<c01ac9d0>] (dbs_check_cpu+0x324/0x340)
[ 2.684582] [<c01ac9d0>] (dbs_check_cpu+0x324/0x340) from [<c01aca40>] (do_dbs_timer+0x54/0xf4)
[ 2.693277] [<c01aca40>] (do_dbs_timer+0x54/0xf4) from [<c00369a8>] (process_one_work+0x1d4/0x320)
[ 2.702225] [<c00369a8>] (process_one_work+0x1d4/0x320) from [<c0036f34>] (worker_thread+0x134/0x230)
[ 2.711437] [<c0036f34>] (worker_thread+0x134/0x230) from [<c003add0>] (kthread+0x80/0x8c)
[ 2.719700] [<c003add0>] (kthread+0x80/0x8c) from [<c000ebf4>] (kernel_thread_exit+0x0/0x8)
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
[olof: fixed calculation of printed values]
Signed-off-by: Olof Johansson <olof@lixom.net>
Enhance the driver to dynamically allocate the base IRQ number, and
create an IRQ domain for itself. The use of an IRQ domain ensures that
any device tree node interrupts properties are correctly parsed.
Describe interrupt-related properties in the device tree binding docs,
and the contents of "child" node interrupts property.
Update tegra*.dtsi to specify the required interrupt-related properties.
Finally, remove the definition of TEGRA_GPIO_TO_IRQ; this macro no longer
gives correct results since the IRQ numbers for GPIOs are dynamically
allocated.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Olof Johansson <olof@lixom.net>
Replace compile-time usage of TEGRA_GPIO_TO_IRQ with run-time calls to
gpio_to_irq(). This will allow the base IRQ number for the Tegra GPIO
driver to be dynamically allocated in a later patch.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Olof Johansson <olof@lixom.net>
uncompress.h now saves the selected UART's physical address in Tegra's
IRAM, along with a cookie to indicate validity.
The first time it's run, macro addruart in debug-macro.S looks for this
cookie, and if it's present, uses the UART address stored there. If not,
the static value TEGRA_DEBUG_UART_BASE is used, as was previous behaviour.
The static behaviour will thus be used when not booting using a zImage.
This work was inspired by work by Doug Anderson <dianders@chromium.org>;
see http://lkml.org/lkml/2011/9/26/284. However, this patch relies on
the data passing describe above, rather than duplicating the UART
selection logic in debug-macro.S; the latest selection logic is more
complex due to the need to check reset/clock bits too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Doug Anderson <dianders@chromium.org>
Acked-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
With this change we automatically detect which UART to use for
for printing during decompression. The detection involves coordination
with the bootloader: it's expected that the bootloader will leave a
'D' (for [D]ebug) in the UART scratchpad register for whichever UART we
should use for debugging.
If we don't find any such UART, we fall back to the UART that was
specified during config time: CONFIG_TEGRA_DEBUG_UART_XXX.
As a side effect of this change, uncompress debug messages will work
if you've specified CONFIG_TEGRA_DEBUG_UART_NONE, provided the
bootloader obeys the protocol.
This change is in line with what is documented in
Documentation/arm/Booting.
Other approaches considered:
* Hardcode based on machine ID (as many other ARM boards do).
OK, but nice to not have yet another place to add per-board
code. Better to have bootloader parse device tree and pass us
this info.
* Check for TXE bit (like SA1110). Nice (and doesn't require
a bootloader change), but a little less explicit. Also: if
bootloader (for some reason) uses another UART, it needs to
remember to turn it off before jumping to the kernel or we may
print to it. NOTE: adapting this patch to check TXE too would
be easy if desired.
Signed-off-by: Doug Anderson <dianders@chromium.org>
[swarren: Added clock/reset condition checks]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Doug Anderson <dianders@chromium.org>
Acked-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
On Tegra20, the UART clock runs at 216MHz, whereas on Tegra30 it runs at
408MHz. Modify arch_decomp_setup() to detect Tegra20-vs-Tegra30 at run-
time, and program the correct divisor.
This makes uncompressor messages work correctly on Tegra30. This also
fixes early printk, assuming zImage is used and this setup code runs.
v2: Use CHIPID register to differentiate between chips, rather than a
GIC register. This should be more future-proof. Volatile is required
to prevent the compiler transforming the 32-bit apb_misc register read
into an 8-bit read of address 1 higher, since the HW only supports 32-
bit accesses, and will hang on an 8-bit access.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
In order to read an accurate channel transfer count
from the APB DMA engine, the DMA controller must be
paused first.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add device tree support to the emc driver, filling in the platform data
based on the DT bindings.
Changes since v1:
* Unmangled some messed up patch squashes, moving changes to earlier patches
* Flipped an of_property_read_u32 return value test
* Clarified clock settings message on case where no table is provided
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Stephen Warren <swarren@nvidia.com>
This is the first step in making it device-tree aware and get rid of the
in-kernel EMC tables (of which there are none in mainline, thankfully).
Changes since v3:
* moved to devm_request_and_ioremap() in probe()
Changes since v2:
* D'oh -- missed a couple of variables that were added, never used and then
later removed in a later patch.
Changes since v1:
* Fixed messed up indentation
* Removed code that should be gone (was added here and removed later in series)
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Stephen Warren <swarren@nvidia.com>
Add function to get chip revision, and print it out at boot time.
Restructure the fuse access to just use cached variables instead
of always reading the fuses, and export those variables directly
instead of using accessor functions.
Add a SKU ID table of currently known values.
Based on code originally by Colin Cross <ccross@android.com>.
Changes since v1:
* Add A01 minor rev support
* Don't decode for A03p on anything but T2x
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tegra2 hangs if APB registers are accessed from the cpu during an
apb dma operation. The workaround is to use apb dma to read/write the
registers instead.
There is a dependency loop between fuses, clocks, and APBDMA. If dma
is enabled, fuse reads must go through APBDMA to avoid corruption due
to a hw bug. APBDMA requires a clock to be enabled. Clocks must read
a fuse to determine allowable cpu frequencies.
Separate out the fuse DMA initialization, and allow the fuse read
and write functions to be called without using DMA before the DMA
initialization has been completed. Access to the fuses before APBDMA
is initialized won't hit the hardware bug because nothing else can be
using DMA.
Original fuse registar access code from Varun Wadekar
<vwadekar@nvidia.com>, improved by Colin Cross <ccross@android.com>
and later moved to separate driver by Jon Mayo <jmayo@nvidia.com>.
Major refactoring/cleanup by Olof Johansson <olof@lixom.net>.
Changes since v1:
* fix 'return false' on error condition
* dequeue dma ops in case of timeout
From: Jon Mayo <jmayo@nvidia.com>.
Signed-off-by: Jon Mayo <jmayo@nvidia.com>.
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Stephen Warren <swarren@nvidia.com>
Since we'll do opportunistic allocations before the dma subsystem is
enabled we want just silent failures and retries instead.
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch is adding device tree support of headset autodetection on PAZ00 board.
Signed-off-by: Leon Romanovsky <leon@leon.nu>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds initial device tree support of ALC5632 sound codec and
machine driver for PAZ00 board. The implementation is based on the WM8903 codec.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Leon Romanovsky <leon@leon.nu>
Signed-off-by: Olof Johansson <olof@lixom.net>
