Merge branches 'for-next/acpi', 'for-next/boot', 'for-next/bpf', 'for-next/cpuinfo', 'for-next/fpsimd', 'for-next/misc', 'for-next/mm', 'for-next/pci', 'for-next/perf', 'for-next/ptrauth', 'for-next/sdei', 'for-next/selftests', 'for-next/stacktrace', 'for-next/svm', 'for-next/topology', 'for-next/tpyos' and 'for-next/vdso' into for-next/core
Remove unused functions and parameters from ACPI IORT code.
(Zenghui Yu via Lorenzo Pieralisi)
* for-next/acpi:
ACPI/IORT: Remove the unused inline functions
ACPI/IORT: Drop the unused @ops of iort_add_device_replay()
Remove redundant code and fix documentation of caching behaviour for the
HVC_SOFT_RESTART hypercall.
(Pingfan Liu)
* for-next/boot:
Documentation/kvm/arm: improve description of HVC_SOFT_RESTART
arm64/relocate_kernel: remove redundant code
Improve reporting of unexpected kernel traps due to BPF JIT failure.
(Will Deacon)
* for-next/bpf:
arm64: Improve diagnostics when trapping BRK with FAULT_BRK_IMM
Improve robustness of user-visible HWCAP strings and their corresponding
numerical constants.
(Anshuman Khandual)
* for-next/cpuinfo:
arm64/cpuinfo: Define HWCAP name arrays per their actual bit definitions
Cleanups to handling of SVE and FPSIMD register state in preparation
for potential future optimisation of handling across syscalls.
(Julien Grall)
* for-next/fpsimd:
arm64/sve: Implement a helper to load SVE registers from FPSIMD state
arm64/sve: Implement a helper to flush SVE registers
arm64/fpsimdmacros: Allow the macro "for" to be used in more cases
arm64/fpsimdmacros: Introduce a macro to update ZCR_EL1.LEN
arm64/signal: Update the comment in preserve_sve_context
arm64/fpsimd: Update documentation of do_sve_acc
Miscellaneous changes.
(Tian Tao and others)
* for-next/misc:
arm64/mm: return cpu_all_mask when node is NUMA_NO_NODE
arm64: mm: Fix missing-prototypes in pageattr.c
arm64/fpsimd: Fix missing-prototypes in fpsimd.c
arm64: hibernate: Remove unused including <linux/version.h>
arm64/mm: Refactor {pgd, pud, pmd, pte}_ERROR()
arm64: Remove the unused include statements
arm64: get rid of TEXT_OFFSET
arm64: traps: Add str of description to panic() in die()
Memory management updates and cleanups.
(Anshuman Khandual and others)
* for-next/mm:
arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
arm64: mm: Make flush_tlb_fix_spurious_fault() a no-op
arm64/mm: Unify CONT_PMD_SHIFT
arm64/mm: Unify CONT_PTE_SHIFT
arm64/mm: Remove CONT_RANGE_OFFSET
arm64/mm: Enable THP migration
arm64/mm: Change THP helpers to comply with generic MM semantics
arm64/mm/ptdump: Add address markers for BPF regions
Allow prefetchable PCI BARs to be exposed to userspace using normal
non-cacheable mappings.
(Clint Sbisa)
* for-next/pci:
arm64: Enable PCI write-combine resources under sysfs
Perf/PMU driver updates.
(Julien Thierry and others)
* for-next/perf:
perf: arm-cmn: Fix conversion specifiers for node type
perf: arm-cmn: Fix unsigned comparison to less than zero
arm_pmu: arm64: Use NMIs for PMU
arm_pmu: Introduce pmu_irq_ops
KVM: arm64: pmu: Make overflow handler NMI safe
arm64: perf: Defer irq_work to IPI_IRQ_WORK
arm64: perf: Remove PMU locking
arm64: perf: Avoid PMXEV* indirection
arm64: perf: Add missing ISB in armv8pmu_enable_counter()
perf: Add Arm CMN-600 PMU driver
perf: Add Arm CMN-600 DT binding
arm64: perf: Add support caps under sysfs
drivers/perf: thunderx2_pmu: Fix memory resource error handling
drivers/perf: xgene_pmu: Fix uninitialized resource struct
perf: arm_dsu: Support DSU ACPI devices
arm64: perf: Remove unnecessary event_idx check
drivers/perf: hisi: Add missing include of linux/module.h
arm64: perf: Add general hardware LLC events for PMUv3
Support for the Armv8.3 Pointer Authentication enhancements.
(By Amit Daniel Kachhap)
* for-next/ptrauth:
arm64: kprobe: clarify the comment of steppable hint instructions
arm64: kprobe: disable probe of fault prone ptrauth instruction
arm64: cpufeature: Modify address authentication cpufeature to exact
arm64: ptrauth: Introduce Armv8.3 pointer authentication enhancements
arm64: traps: Allow force_signal_inject to pass esr error code
arm64: kprobe: add checks for ARMv8.3-PAuth combined instructions
Tonnes of cleanup to the SDEI driver.
(Gavin Shan)
* for-next/sdei:
firmware: arm_sdei: Remove _sdei_event_unregister()
firmware: arm_sdei: Remove _sdei_event_register()
firmware: arm_sdei: Introduce sdei_do_local_call()
firmware: arm_sdei: Cleanup on cross call function
firmware: arm_sdei: Remove while loop in sdei_event_unregister()
firmware: arm_sdei: Remove while loop in sdei_event_register()
firmware: arm_sdei: Remove redundant error message in sdei_probe()
firmware: arm_sdei: Remove duplicate check in sdei_get_conduit()
firmware: arm_sdei: Unregister driver on error in sdei_init()
firmware: arm_sdei: Avoid nested statements in sdei_init()
firmware: arm_sdei: Retrieve event number from event instance
firmware: arm_sdei: Common block for failing path in sdei_event_create()
firmware: arm_sdei: Remove sdei_is_err()
Selftests for Pointer Authentication and FPSIMD/SVE context-switching.
(Mark Brown and Boyan Karatotev)
* for-next/selftests:
selftests: arm64: Add build and documentation for FP tests
selftests: arm64: Add wrapper scripts for stress tests
selftests: arm64: Add utility to set SVE vector lengths
selftests: arm64: Add stress tests for FPSMID and SVE context switching
selftests: arm64: Add test for the SVE ptrace interface
selftests: arm64: Test case for enumeration of SVE vector lengths
kselftests/arm64: add PAuth tests for single threaded consistency and differently initialized keys
kselftests/arm64: add PAuth test for whether exec() changes keys
kselftests/arm64: add nop checks for PAuth tests
kselftests/arm64: add a basic Pointer Authentication test
Implementation of ARCH_STACKWALK for unwinding.
(Mark Brown)
* for-next/stacktrace:
arm64: Move console stack display code to stacktrace.c
arm64: stacktrace: Convert to ARCH_STACKWALK
arm64: stacktrace: Make stack walk callback consistent with generic code
stacktrace: Remove reliable argument from arch_stack_walk() callback
Support for ASID pinning, which is required when sharing page-tables with
the SMMU.
(Jean-Philippe Brucker)
* for-next/svm:
arm64: cpufeature: Export symbol read_sanitised_ftr_reg()
arm64: mm: Pin down ASIDs for sharing mm with devices
Rely on firmware tables for establishing CPU topology.
(Valentin Schneider)
* for-next/topology:
arm64: topology: Stop using MPIDR for topology information
Spelling fixes.
(Xiaoming Ni and Yanfei Xu)
* for-next/tpyos:
arm64/numa: Fix a typo in comment of arm64_numa_init
arm64: fix some spelling mistakes in the comments by codespell
vDSO cleanups.
(Will Deacon)
* for-next/vdso:
arm64: vdso: Fix unusual formatting in *setup_additional_pages()
arm64: vdso32: Remove a bunch of #ifdef CONFIG_COMPAT_VDSO guards
This commit is contained in:
Will Deacon
@@ -13,8 +13,7 @@
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#define MAX_FDT_SIZE SZ_2M
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/*
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* arm64 requires the kernel image to placed
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* TEXT_OFFSET bytes beyond a 2 MB aligned base
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* arm64 requires the kernel image to placed at a 2 MB aligned base address
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*/
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#define MIN_KIMG_ALIGN SZ_2M
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@@ -21,7 +21,7 @@
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* mechanism for doing so, tests whether it is possible to boot
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* the given CPU.
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* @cpu_boot: Boots a cpu into the kernel.
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* @cpu_postboot: Optionally, perform any post-boot cleanup or necesary
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* @cpu_postboot: Optionally, perform any post-boot cleanup or necessary
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* synchronisation. Called from the cpu being booted.
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* @cpu_can_disable: Determines whether a CPU can be disabled based on
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* mechanism-specific information.
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@@ -358,7 +358,7 @@ static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
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}
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/*
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* Generic helper for handling capabilties with multiple (match,enable) pairs
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* Generic helper for handling capabilities with multiple (match,enable) pairs
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* of call backs, sharing the same capability bit.
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* Iterate over each entry to see if at least one matches.
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*/
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@@ -35,7 +35,9 @@
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#define ESR_ELx_EC_SYS64 (0x18)
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#define ESR_ELx_EC_SVE (0x19)
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#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
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/* Unallocated EC: 0x1b - 0x1E */
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/* Unallocated EC: 0x1B */
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#define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */
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/* Unallocated EC: 0x1D - 0x1E */
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#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
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#define ESR_ELx_EC_IABT_LOW (0x20)
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#define ESR_ELx_EC_IABT_CUR (0x21)
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@@ -47,4 +47,5 @@ void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr);
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void do_cp15instr(unsigned int esr, struct pt_regs *regs);
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void do_el0_svc(struct pt_regs *regs);
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void do_el0_svc_compat(struct pt_regs *regs);
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void do_ptrauth_fault(struct pt_regs *regs, unsigned int esr);
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#endif /* __ASM_EXCEPTION_H */
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@@ -22,6 +22,15 @@ struct exception_table_entry
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#define ARCH_HAS_RELATIVE_EXTABLE
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static inline bool in_bpf_jit(struct pt_regs *regs)
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{
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if (!IS_ENABLED(CONFIG_BPF_JIT))
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return false;
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return regs->pc >= BPF_JIT_REGION_START &&
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regs->pc < BPF_JIT_REGION_END;
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}
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#ifdef CONFIG_BPF_JIT
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int arm64_bpf_fixup_exception(const struct exception_table_entry *ex,
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struct pt_regs *regs);
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@@ -69,6 +69,9 @@ static inline void *sve_pffr(struct thread_struct *thread)
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extern void sve_save_state(void *state, u32 *pfpsr);
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extern void sve_load_state(void const *state, u32 const *pfpsr,
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unsigned long vq_minus_1);
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extern void sve_flush_live(void);
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extern void sve_load_from_fpsimd_state(struct user_fpsimd_state const *state,
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unsigned long vq_minus_1);
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extern unsigned int sve_get_vl(void);
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struct arm64_cpu_capabilities;
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@@ -164,25 +164,59 @@
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| ((\np) << 5)
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.endm
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/* PFALSE P\np.B */
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.macro _sve_pfalse np
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_sve_check_preg \np
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.inst 0x2518e400 \
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| (\np)
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.endm
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.macro __for from:req, to:req
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.if (\from) == (\to)
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_for__body \from
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_for__body %\from
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.else
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__for \from, (\from) + ((\to) - (\from)) / 2
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__for (\from) + ((\to) - (\from)) / 2 + 1, \to
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__for %\from, %((\from) + ((\to) - (\from)) / 2)
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__for %((\from) + ((\to) - (\from)) / 2 + 1), %\to
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.endif
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.endm
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.macro _for var:req, from:req, to:req, insn:vararg
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.macro _for__body \var:req
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.noaltmacro
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\insn
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.altmacro
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.endm
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.altmacro
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__for \from, \to
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.noaltmacro
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.purgem _for__body
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.endm
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/* Update ZCR_EL1.LEN with the new VQ */
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.macro sve_load_vq xvqminus1, xtmp, xtmp2
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mrs_s \xtmp, SYS_ZCR_EL1
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bic \xtmp2, \xtmp, ZCR_ELx_LEN_MASK
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orr \xtmp2, \xtmp2, \xvqminus1
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cmp \xtmp2, \xtmp
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b.eq 921f
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msr_s SYS_ZCR_EL1, \xtmp2 //self-synchronising
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921:
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.endm
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/* Preserve the first 128-bits of Znz and zero the rest. */
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.macro _sve_flush_z nz
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_sve_check_zreg \nz
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mov v\nz\().16b, v\nz\().16b
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.endm
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.macro sve_flush
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_for n, 0, 31, _sve_flush_z \n
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_for n, 0, 15, _sve_pfalse \n
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_sve_wrffr 0
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.endm
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.macro sve_save nxbase, xpfpsr, nxtmp
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_for n, 0, 31, _sve_str_v \n, \nxbase, \n - 34
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_for n, 0, 15, _sve_str_p \n, \nxbase, \n - 16
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@@ -197,13 +231,7 @@
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.endm
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.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp, xtmp2
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mrs_s x\nxtmp, SYS_ZCR_EL1
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bic \xtmp2, x\nxtmp, ZCR_ELx_LEN_MASK
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orr \xtmp2, \xtmp2, \xvqminus1
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cmp \xtmp2, x\nxtmp
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b.eq 921f
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msr_s SYS_ZCR_EL1, \xtmp2 // self-synchronising
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921:
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sve_load_vq \xvqminus1, x\nxtmp, \xtmp2
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_for n, 0, 31, _sve_ldr_v \n, \nxbase, \n - 34
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_sve_ldr_p 0, \nxbase
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_sve_wrffr 0
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@@ -8,18 +8,27 @@
|
||||
#include <uapi/asm/hwcap.h>
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#include <asm/cpufeature.h>
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||||
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#define COMPAT_HWCAP_SWP (1 << 0)
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#define COMPAT_HWCAP_HALF (1 << 1)
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#define COMPAT_HWCAP_THUMB (1 << 2)
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#define COMPAT_HWCAP_26BIT (1 << 3)
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#define COMPAT_HWCAP_FAST_MULT (1 << 4)
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||||
#define COMPAT_HWCAP_FPA (1 << 5)
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#define COMPAT_HWCAP_VFP (1 << 6)
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#define COMPAT_HWCAP_EDSP (1 << 7)
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#define COMPAT_HWCAP_JAVA (1 << 8)
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#define COMPAT_HWCAP_IWMMXT (1 << 9)
|
||||
#define COMPAT_HWCAP_CRUNCH (1 << 10)
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#define COMPAT_HWCAP_THUMBEE (1 << 11)
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#define COMPAT_HWCAP_NEON (1 << 12)
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#define COMPAT_HWCAP_VFPv3 (1 << 13)
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#define COMPAT_HWCAP_VFPV3D16 (1 << 14)
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#define COMPAT_HWCAP_TLS (1 << 15)
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#define COMPAT_HWCAP_VFPv4 (1 << 16)
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#define COMPAT_HWCAP_IDIVA (1 << 17)
|
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#define COMPAT_HWCAP_IDIVT (1 << 18)
|
||||
#define COMPAT_HWCAP_IDIV (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT)
|
||||
#define COMPAT_HWCAP_VFPD32 (1 << 19)
|
||||
#define COMPAT_HWCAP_LPAE (1 << 20)
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||||
#define COMPAT_HWCAP_EVTSTRM (1 << 21)
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||||
|
||||
|
||||
@@ -359,9 +359,13 @@ __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
|
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__AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
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__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
|
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__AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
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__AARCH64_INSN_FUNCS(br_auth, 0xFEFFF800, 0xD61F0800)
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__AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
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__AARCH64_INSN_FUNCS(blr_auth, 0xFEFFF800, 0xD63F0800)
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__AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
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__AARCH64_INSN_FUNCS(ret_auth, 0xFFFFFBFF, 0xD65F0BFF)
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__AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0)
|
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__AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF)
|
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__AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000)
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__AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F)
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__AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000)
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@@ -86,7 +86,7 @@
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+ EARLY_PGDS((vstart), (vend)) /* each PGDIR needs a next level page table */ \
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+ EARLY_PUDS((vstart), (vend)) /* each PUD needs a next level page table */ \
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+ EARLY_PMDS((vstart), (vend))) /* each PMD needs a next level page table */
|
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#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR + TEXT_OFFSET, _end))
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#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end))
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#define IDMAP_DIR_SIZE (IDMAP_PGTABLE_LEVELS * PAGE_SIZE)
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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@@ -66,7 +66,7 @@
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* TWI: Trap WFI
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* TIDCP: Trap L2CTLR/L2ECTLR
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* BSU_IS: Upgrade barriers to the inner shareable domain
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* FB: Force broadcast of all maintainance operations
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* FB: Force broadcast of all maintenance operations
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* AMO: Override CPSR.A and enable signaling with VA
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* IMO: Override CPSR.I and enable signaling with VI
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* FMO: Override CPSR.F and enable signaling with VF
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||||
@@ -169,7 +169,7 @@ extern s64 memstart_addr;
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/* PHYS_OFFSET - the physical address of the start of memory. */
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#define PHYS_OFFSET ({ VM_BUG_ON(memstart_addr & 1); memstart_addr; })
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||||
/* the virtual base of the kernel image (minus TEXT_OFFSET) */
|
||||
/* the virtual base of the kernel image */
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extern u64 kimage_vaddr;
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||||
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||||
/* the offset between the kernel virtual and physical mappings */
|
||||
|
||||
@@ -17,11 +17,14 @@
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||||
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||||
#ifndef __ASSEMBLY__
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#include <linux/refcount.h>
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||||
|
||||
typedef struct {
|
||||
atomic64_t id;
|
||||
#ifdef CONFIG_COMPAT
|
||||
void *sigpage;
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||||
#endif
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||||
refcount_t pinned;
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||||
void *vdso;
|
||||
unsigned long flags;
|
||||
} mm_context_t;
|
||||
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||||
@@ -177,7 +177,13 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp)
|
||||
#define destroy_context(mm) do { } while(0)
|
||||
void check_and_switch_context(struct mm_struct *mm);
|
||||
|
||||
#define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; })
|
||||
static inline int
|
||||
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
|
||||
{
|
||||
atomic64_set(&mm->context.id, 0);
|
||||
refcount_set(&mm->context.pinned, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
|
||||
static inline void update_saved_ttbr0(struct task_struct *tsk,
|
||||
@@ -248,6 +254,9 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
void verify_cpu_asid_bits(void);
|
||||
void post_ttbr_update_workaround(void);
|
||||
|
||||
unsigned long arm64_mm_context_get(struct mm_struct *mm);
|
||||
void arm64_mm_context_put(struct mm_struct *mm);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* !__ASM_MMU_CONTEXT_H */
|
||||
|
||||
@@ -25,6 +25,9 @@ const struct cpumask *cpumask_of_node(int node);
|
||||
/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
|
||||
static inline const struct cpumask *cpumask_of_node(int node)
|
||||
{
|
||||
if (node == NUMA_NO_NODE)
|
||||
return cpu_all_mask;
|
||||
|
||||
return node_to_cpumask_map[node];
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -11,13 +11,8 @@
|
||||
#include <linux/const.h>
|
||||
|
||||
/* PAGE_SHIFT determines the page size */
|
||||
/* CONT_SHIFT determines the number of pages which can be tracked together */
|
||||
#define PAGE_SHIFT CONFIG_ARM64_PAGE_SHIFT
|
||||
#define CONT_SHIFT CONFIG_ARM64_CONT_SHIFT
|
||||
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
|
||||
#define PAGE_MASK (~(PAGE_SIZE-1))
|
||||
|
||||
#define CONT_SIZE (_AC(1, UL) << (CONT_SHIFT + PAGE_SHIFT))
|
||||
#define CONT_MASK (~(CONT_SIZE-1))
|
||||
|
||||
#endif /* __ASM_PAGE_DEF_H */
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
#define pcibios_assign_all_busses() \
|
||||
(pci_has_flag(PCI_REASSIGN_ALL_BUS))
|
||||
|
||||
#define arch_can_pci_mmap_wc() 1
|
||||
#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
|
||||
|
||||
extern int isa_dma_bridge_buggy;
|
||||
|
||||
@@ -236,6 +236,9 @@
|
||||
#define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
|
||||
#define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
|
||||
|
||||
/* PMMIR_EL1.SLOTS mask */
|
||||
#define ARMV8_PMU_SLOTS_MASK 0xff
|
||||
|
||||
#ifdef CONFIG_PERF_EVENTS
|
||||
struct pt_regs;
|
||||
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
|
||||
|
||||
@@ -81,25 +81,15 @@
|
||||
/*
|
||||
* Contiguous page definitions.
|
||||
*/
|
||||
#ifdef CONFIG_ARM64_64K_PAGES
|
||||
#define CONT_PTE_SHIFT (5 + PAGE_SHIFT)
|
||||
#define CONT_PMD_SHIFT (5 + PMD_SHIFT)
|
||||
#elif defined(CONFIG_ARM64_16K_PAGES)
|
||||
#define CONT_PTE_SHIFT (7 + PAGE_SHIFT)
|
||||
#define CONT_PMD_SHIFT (5 + PMD_SHIFT)
|
||||
#else
|
||||
#define CONT_PTE_SHIFT (4 + PAGE_SHIFT)
|
||||
#define CONT_PMD_SHIFT (4 + PMD_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONT_PTE_SHIFT (CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
|
||||
#define CONT_PTES (1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
|
||||
#define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE)
|
||||
#define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1))
|
||||
|
||||
#define CONT_PMD_SHIFT (CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
|
||||
#define CONT_PMDS (1 << (CONT_PMD_SHIFT - PMD_SHIFT))
|
||||
#define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE)
|
||||
#define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1))
|
||||
/* the numerical offset of the PTE within a range of CONT_PTES */
|
||||
#define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))
|
||||
|
||||
/*
|
||||
* Hardware page table definitions.
|
||||
|
||||
@@ -19,6 +19,13 @@
|
||||
#define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
|
||||
#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
|
||||
|
||||
/*
|
||||
* This bit indicates that the entry is present i.e. pmd_page()
|
||||
* still points to a valid huge page in memory even if the pmd
|
||||
* has been invalidated.
|
||||
*/
|
||||
#define PMD_PRESENT_INVALID (_AT(pteval_t, 1) << 59) /* only when !PMD_SECT_VALID */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/cpufeature.h>
|
||||
|
||||
@@ -35,11 +35,6 @@
|
||||
|
||||
extern struct page *vmemmap;
|
||||
|
||||
extern void __pte_error(const char *file, int line, unsigned long val);
|
||||
extern void __pmd_error(const char *file, int line, unsigned long val);
|
||||
extern void __pud_error(const char *file, int line, unsigned long val);
|
||||
extern void __pgd_error(const char *file, int line, unsigned long val);
|
||||
|
||||
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
||||
#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
|
||||
|
||||
@@ -50,6 +45,14 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
|
||||
__flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
|
||||
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
||||
|
||||
/*
|
||||
* Outside of a few very special situations (e.g. hibernation), we always
|
||||
* use broadcast TLB invalidation instructions, therefore a spurious page
|
||||
* fault on one CPU which has been handled concurrently by another CPU
|
||||
* does not need to perform additional invalidation.
|
||||
*/
|
||||
#define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
|
||||
|
||||
/*
|
||||
* ZERO_PAGE is a global shared page that is always zero: used
|
||||
* for zero-mapped memory areas etc..
|
||||
@@ -57,7 +60,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
|
||||
extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
|
||||
#define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
|
||||
|
||||
#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
|
||||
#define pte_ERROR(e) \
|
||||
pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
|
||||
|
||||
/*
|
||||
* Macros to convert between a physical address and its placement in a
|
||||
@@ -145,6 +149,18 @@ static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
|
||||
return pte;
|
||||
}
|
||||
|
||||
static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
|
||||
{
|
||||
pmd_val(pmd) &= ~pgprot_val(prot);
|
||||
return pmd;
|
||||
}
|
||||
|
||||
static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
|
||||
{
|
||||
pmd_val(pmd) |= pgprot_val(prot);
|
||||
return pmd;
|
||||
}
|
||||
|
||||
static inline pte_t pte_wrprotect(pte_t pte)
|
||||
{
|
||||
pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
|
||||
@@ -363,15 +379,24 @@ static inline int pmd_protnone(pmd_t pmd)
|
||||
}
|
||||
#endif
|
||||
|
||||
#define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
|
||||
|
||||
static inline int pmd_present(pmd_t pmd)
|
||||
{
|
||||
return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
|
||||
}
|
||||
|
||||
/*
|
||||
* THP definitions.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
||||
#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
|
||||
static inline int pmd_trans_huge(pmd_t pmd)
|
||||
{
|
||||
return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
|
||||
}
|
||||
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
||||
|
||||
#define pmd_present(pmd) pte_present(pmd_pte(pmd))
|
||||
#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
|
||||
#define pmd_young(pmd) pte_young(pmd_pte(pmd))
|
||||
#define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
|
||||
@@ -381,7 +406,14 @@ static inline int pmd_protnone(pmd_t pmd)
|
||||
#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
|
||||
#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
|
||||
#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
|
||||
#define pmd_mkinvalid(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID))
|
||||
|
||||
static inline pmd_t pmd_mkinvalid(pmd_t pmd)
|
||||
{
|
||||
pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
|
||||
pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
|
||||
|
||||
return pmd;
|
||||
}
|
||||
|
||||
#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
|
||||
|
||||
@@ -541,7 +573,8 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd)
|
||||
|
||||
#if CONFIG_PGTABLE_LEVELS > 2
|
||||
|
||||
#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
|
||||
#define pmd_ERROR(e) \
|
||||
pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
|
||||
|
||||
#define pud_none(pud) (!pud_val(pud))
|
||||
#define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
|
||||
@@ -608,7 +641,8 @@ static inline unsigned long pud_page_vaddr(pud_t pud)
|
||||
|
||||
#if CONFIG_PGTABLE_LEVELS > 3
|
||||
|
||||
#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
|
||||
#define pud_ERROR(e) \
|
||||
pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
|
||||
|
||||
#define p4d_none(p4d) (!p4d_val(p4d))
|
||||
#define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
|
||||
@@ -667,7 +701,8 @@ static inline unsigned long p4d_page_vaddr(p4d_t p4d)
|
||||
|
||||
#endif /* CONFIG_PGTABLE_LEVELS > 3 */
|
||||
|
||||
#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
|
||||
#define pgd_ERROR(e) \
|
||||
pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
|
||||
|
||||
#define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
|
||||
#define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
|
||||
@@ -847,6 +882,11 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
|
||||
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
||||
#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
|
||||
|
||||
#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
|
||||
#define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
|
||||
#define __swp_entry_to_pmd(swp) __pmd((swp).val)
|
||||
#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
|
||||
|
||||
/*
|
||||
* Ensure that there are not more swap files than can be encoded in the kernel
|
||||
* PTEs.
|
||||
|
||||
@@ -63,7 +63,7 @@ struct stackframe {
|
||||
|
||||
extern int unwind_frame(struct task_struct *tsk, struct stackframe *frame);
|
||||
extern void walk_stackframe(struct task_struct *tsk, struct stackframe *frame,
|
||||
int (*fn)(struct stackframe *, void *), void *data);
|
||||
bool (*fn)(void *, unsigned long), void *data);
|
||||
extern void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
|
||||
const char *loglvl);
|
||||
|
||||
|
||||
@@ -321,6 +321,8 @@
|
||||
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
|
||||
#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
|
||||
|
||||
#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
|
||||
|
||||
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
|
||||
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
|
||||
|
||||
@@ -636,14 +638,22 @@
|
||||
#define ID_AA64ISAR1_APA_SHIFT 4
|
||||
#define ID_AA64ISAR1_DPB_SHIFT 0
|
||||
|
||||
#define ID_AA64ISAR1_APA_NI 0x0
|
||||
#define ID_AA64ISAR1_APA_ARCHITECTED 0x1
|
||||
#define ID_AA64ISAR1_API_NI 0x0
|
||||
#define ID_AA64ISAR1_API_IMP_DEF 0x1
|
||||
#define ID_AA64ISAR1_GPA_NI 0x0
|
||||
#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
|
||||
#define ID_AA64ISAR1_GPI_NI 0x0
|
||||
#define ID_AA64ISAR1_GPI_IMP_DEF 0x1
|
||||
#define ID_AA64ISAR1_APA_NI 0x0
|
||||
#define ID_AA64ISAR1_APA_ARCHITECTED 0x1
|
||||
#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2
|
||||
#define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3
|
||||
#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4
|
||||
#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5
|
||||
#define ID_AA64ISAR1_API_NI 0x0
|
||||
#define ID_AA64ISAR1_API_IMP_DEF 0x1
|
||||
#define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2
|
||||
#define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3
|
||||
#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4
|
||||
#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5
|
||||
#define ID_AA64ISAR1_GPA_NI 0x0
|
||||
#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
|
||||
#define ID_AA64ISAR1_GPI_NI 0x0
|
||||
#define ID_AA64ISAR1_GPI_IMP_DEF 0x1
|
||||
|
||||
/* id_aa64pfr0 */
|
||||
#define ID_AA64PFR0_CSV3_SHIFT 60
|
||||
|
||||
@@ -24,7 +24,7 @@ struct undef_hook {
|
||||
|
||||
void register_undef_hook(struct undef_hook *hook);
|
||||
void unregister_undef_hook(struct undef_hook *hook);
|
||||
void force_signal_inject(int signal, int code, unsigned long address);
|
||||
void force_signal_inject(int signal, int code, unsigned long address, unsigned int err);
|
||||
void arm64_notify_segfault(unsigned long addr);
|
||||
void arm64_force_sig_fault(int signo, int code, void __user *addr, const char *str);
|
||||
void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, const char *str);
|
||||
|
||||
Reference in New Issue
Block a user